Standard cell automated layout for a CMOS 50 MHz 8 × 8 bit pipelined parallel dadda multiplier

An 8 × 8 pipelined parallel multiplier which uses the Dadda scheme is presented. The multiplier has been implemented in a 3-μm n-well CMOS process with two layers of metal using a standard cell automatic placement and routing program. The design uses a form of pipelined carry look-ahead adder in the final stage of summation, thus providing a significant contribution to the high performance of the multiplier. The design is expected to operate at a clock frequency of at least 50 MHz and has a flush time of seven clock cycles. The design illustrates a possible method of implementing an irregular architecture in VLSI using multiple levels of low-resistance, low-capacitance interconnect and automated layout techniques.

Using strong sustainability to optimize electricity generation fuel mixes

This work represents a contribution to the field of sustainable electricity system design by using an optimization tool to specify the final mix composition, subject to the constraints of: emissions that are within the biocapacity of the region; a diverse and robust electricity supply system; and supply that at least meets current demand. The 25-country European Union (EU-25) is used as a case study. All the goals, save diversity, can be met by re-structuring the current fuel mix, thus maintaining current consumption levels. The diversity target is only met when consumption is reduced by 10-15% and the constraint on maximum material throughput is relaxed. Re-structuring the mix and reducing consumption is insufficient to achieve a sustainable EU carbon footprint. However, the solution proposed singlehandedly allows the EU to meet its Kyoto emissions target as well as its 2007 policy of a reduction of 20% in greenhouse gas emissions by 2020. © 2007 Elsevier Ltd. All rights reserved.

Thickness control of Molecular Beam Epitaxy grown layers at the 0.01-0.1 monolayer level

Electron tunnelling through semiconductor tunnel barriers is exponentially sensitive to the thickness of the barrier layer, and in the most common system, the AlAs tunnel barrier in GaAs, a one monolayer variation in thickness results in a 300% variation in the tunnelling current for a fixed bias voltage. We use this degree of sensitivity to demonstrate that the level of control at 0.06 monolayer can be achieved in the growth by molecular beam epitaxy, and the geometrical variation of layer thickness across a wafer at the 0.01 monolayer level can be detected.