Tunable electronic transport characteristics of surface-architecture-controlled ZnO nanowire field effect transistors.

Surface-architecture-controlled ZnO nanowires were grown using a vapor transport method on various ZnO buffer film coated c-plane sapphire substrates with or without Au catalysts. The ZnO nanowires that were grown showed two different types of geometric properties: corrugated ZnO nanowires having a relatively smaller diameter and a strong deep-level emission photoluminescence (PL) peak and smooth ZnO nanowires having a relatively larger diameter and a weak deep-level emission PL peak. The surface morphology and size-dependent tunable electronic transport properties of the ZnO nanowires were characterized using a nanowire field effect transistor (FET) device structure. The FETs made from smooth ZnO nanowires with a larger diameter exhibited negative threshold voltages, indicating n-channel depletion-mode behavior, whereas those made from corrugated ZnO nanowires with a smaller diameter had positive threshold voltages, indicating n-channel enhancement-mode behavior.

Hafnia nanoparticles - a model system for graphene growth on a dielectric

We study graphene growth on hafnia (HfO2) nanoparticles by chemical vapour deposition using optical microscopy, high resolution transmission electron microscopy and Raman spectroscopy. We find that monoclinic HfO2 nanoparticles neither reduce to a metal nor form a carbide while nucleating nanometer domain-sized few layer graphene. Hence we regard this as an interesting non-metallic catalyst model system with the potential to explore graphene growth directly on a (high-k) dielectric. HfO2 nanoparticles coated with few layer graphene by atmospheric pressure CVD with methane and hydrogen at 950 °C. (© 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) Graphene growth on hafnia (HfO2) nanoparticles by chemical vapour deposition (CVD) is studied. It is found that monoclinic HfO2 nanoparticles neither reduce to a metal nor form a carbide while nucleating nanometer domain-sized few layer graphene. Hence the authors of this Letter regard this as an interesting non-metallic catalyst model system with the potential to explore graphene growth directly on a (high-k) dielectric. © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

SoC energy savings = reduce+reuse+recycle: A case study using a 660MHz DC-DC converter with integrated output filter

This paper advocates 'reduce, reuse, recycle' as a complete energy savings strategy. While reduction has been common to date, there is growing need to emphasize reuse and recycling as well. We design a DC-DC buck converter to demonstrate the 3 techniques: reduce with low-swing and zero voltage switching (ZVS), reuse with supply stacking, and recycle with regulated delivery of excess energy to the output load. The efficiency gained from these 3 techniques helps offset the loss of operating drivers at very high switching frequencies which are needed to move the output filter completely on-chip. A prototype was fabricated in 0.18μm CMOS, operates at 660MHz, and converts 2.2V to 0.75-1.0V at ∼50mA.1 © 2008 IEEE.