Electronic structure and surface properties of SrBi2Ta2O9 and related oxides

The electronic structure of SrBi2Ta2O9 and related oxides such as SrBi2Nb2O9, Bi2WO6 and Bi3Ti4O12 have been calculated by the tight-binding method. In each case, the band gap is about 4.1 eV and the band edge states occur on the Bi-O layers and consist of mixed O p/Bi s states at the top of the valence band and Bi p states at the bottom of the conduction band. The main difference between the compounds is that Nb 5d and Ti 4d states in the Nb and Ti compounds lie lower than the Ta 6d states in the conduction band. The surface pinning levels are found to pin Schottky barriers 0.8 eV below the conduction band edge.

Standard cell automated layout for a CMOS 50 MHz 8 × 8 bit pipelined parallel dadda multiplier

An 8 × 8 pipelined parallel multiplier which uses the Dadda scheme is presented. The multiplier has been implemented in a 3-μm n-well CMOS process with two layers of metal using a standard cell automatic placement and routing program. The design uses a form of pipelined carry look-ahead adder in the final stage of summation, thus providing a significant contribution to the high performance of the multiplier. The design is expected to operate at a clock frequency of at least 50 MHz and has a flush time of seven clock cycles. The design illustrates a possible method of implementing an irregular architecture in VLSI using multiple levels of low-resistance, low-capacitance interconnect and automated layout techniques.