Standard cell automated layout for a CMOS 50 MHz 8 × 8 bit pipelined parallel dadda multiplier

An 8 × 8 pipelined parallel multiplier which uses the Dadda scheme is presented. The multiplier has been implemented in a 3-μm n-well CMOS process with two layers of metal using a standard cell automatic placement and routing program. The design uses a form of pipelined carry look-ahead adder in the final stage of summation, thus providing a significant contribution to the high performance of the multiplier. The design is expected to operate at a clock frequency of at least 50 MHz and has a flush time of seven clock cycles. The design illustrates a possible method of implementing an irregular architecture in VLSI using multiple levels of low-resistance, low-capacitance interconnect and automated layout techniques.

Options for achieving a 50% cut in industrial carbon emissions by 2050.

Carbon emissions from industry are dominated by production of goods in steel, cement plastic, paper, and aluminum. Demand for these materials is anticipated to double at least by 2050, by which time global carbon emissions must be reduced by at least 50%. To evaluate the challenge of meeting this target the global flows of these materials and their associated emissions are projected to 2050 under five technical scenarios. A reference scenario includes all existing and emerging efficiency measures but cannot provide sufficient reduction. The application of carbon sequestration to primary production proves to be sufficient only for cement The emissions target can always be met by reducing demand, for instance through product life extension, material substitution, or "light-weighting". Reusing components shows significant potential particularly within construction. Radical process innovation may also be possible. The results show that the first two strategies, based on increasing primary production, cannot achieve the required emissions reductions, so should be balanced by the vigorous pursuit of material efficiency to allow provision of increased material services with reduced primary production.

FEC-free 50 m 1.5 Gb/s plastic optical fibre link using CAP modulation for home networks

LED-based carrierless amplitude and phase modulation is investigated for a multi-gigabit plastic optical fibre link. An FPGA-based 1.5 Gbit/s error free transmission over 50 m standard SI-POF using CAP64 is achieved, providing 2.9 dB power margin without forward error correction. © 2012 OSA.

FEC-free 50 m 1.5 Gb/s plastic optical fibre link using CAP modulation for home networks

LED-based carrierless amplitude and phase modulation is investigated for a multi-gigabit plastic optical fibre link. An FPGA-based 1.5 Gbit/s error free transmission over 50 m standard SI-POF using CAP64 is achieved, providing 2.9 dB power margin without forward error correction. © 2012 Optical Society of America.

Modal control of a 50μm core diameter multimode fiber using a spatial light modulator

An iterative, self-correcting system for doing modal control using adaptive optics in a 50μm core diameter multimode fiber (MMF) is designed. It is shown experimentally to reduce the number of modes generated by 300%. © 2006 Optical Society of America.

Modal control of a 50μm core diameter multimode fiber using a spatial light modulator

An iterative, self-correcting system for doing modal control using adaptive optics in a 50μm core diameter multimode fiber (MMF) is designed. It is shown experimentally to reduce the number of modes generated by 300%. © 2006 Optical Society of America.