Liquid crystal based continuous phase retarder: From optically neutral to a quarter waveplate in 200 microseconds

Liquid crystal variable phase retarders have been incorporated into prototype devices for optical communications system applications, both as endless polarization controllers 1,2,3, and as holographic beam steerers 4. Nematic liquid crystals allow continuous control of the degree of retardation induced at relatively slow switching speeds, while ferroelectric liquid crystal based devices allow fast (sub millisecond) switching, but only between two bistable states. The flexoelectro-optic effect 5,6 in short-pitch chiral nematic liquid crystals allows both fast switching of the optic axis and continuous, electric field dependent control of the degree of rotation of the optic axis. A novel geometry for the flexoelectro-optic effect is presented here, in which the helical axis of the chiral nematic is perpendicular to the cell walls (grandjean texture) and the electric field is applied in the plane of the cell. This facilitates deflection of the optic axis of the uniaxial negatively birefringent material from lying along the direction of propagation to having some component in the polarization plane of the light. The device is therefore optically neutral at zero field for telecommunications wavelengths (1550nm), and allows a continuously variable degree of phase excursion to be induced, up to 2π/3 radians achieved so far in a 40μm thick cell. The retardation has been shown both to appear, on application of the field, and disappear on removal, at speeds of 100-500 μs. The direction of deflection of the optic axis is also dependent on the direction of the field, allowing the possibility, in a converging electrode "cartwheel cell", of endless rotation of the liquid crystal waveplate at a higher rate than achievable through dielectric coupling to plain nematic materials.

200-V lateral superjunction LIGBT on partial SOI

This letter presents a novel lateral superjunction lateral insulated-gate bipolar transistor (LIGBT) in partial silicon-on-insulator (SOI) technology in 0.18-μm partial-SOI (PSOI) high-voltage (HV) process. For an n-type superjunction LIGBT, the p-layer in the superjunction drift region not only helps in achieving uniform electric field distribution but also contributes to the on-state current. The superjunction LIGBT successfully achieves a breakdown voltage (BV) of 210 V with an R dson of 765 mΩ ̇ mm 2. It exhibits half the value of specific on-state resistance R dson and three times higher saturation current (I dsat) for the same BV, compared to a comparable lateral superjunction laterally diffused metal-oxide-semiconductor fabricated in the same technology. It also performs well in higher temperature dc operation with 38.8% increase in R dson at 175°C, compared to the room temperature without any degradation in latch-up performance. To realize this device, it only requires one additional mask layer into X-FAB 0.18-μm PSOI HV process. © 2012 IEEE.

200 v superjunction N-type lateral insulated-gate bipolar transistor with improved latch-up characteristics

This paper evaluates the technique used to improve the latching characteristics of the 200 V n-type superjunction (SJ) lateral insulated-gate bipolar transistor (LIGBT) on a partial silicon-on-insulator. SJ IGBT devices are more prone to latch-up than standard IGBTs due to the presence of a strong pnp transistor with the p layer serving as an effective collector of holes. The initial SJ LIGBT design latches at about 23 V with a gate voltage of 5 V with a forward voltage drop (VON) of 2 V at 300 Acm2. The latch-up current density is 1100 Acm2. The latest SJ LIGBT design shows an increase in latch-up voltage close to 100 V without a significant penalty in VON. The latest design shows a latch-up current density of 1195 A cm2. The enhanced robustness against static latch-up leads to a better forward bias safe operating area. © 1963-2012 IEEE.