Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. © 2012 Tan et al.

Modeling bipolar power semiconductor devices gachovska

This book presents physics-based models of bipolar power semiconductor devices and their implementation in MATLAB and Simulink. The devices are subdivided into different regions, and the operation in each region, along with the interactions at the interfaces which are analyzed using basic semiconductor physics equations that govern their behavior. The Fourier series solution is used to solve the ambipolar diffusion equation in the lightly doped drift region of the devices. In addition to the external electrical characteristics, internal physical and electrical information, such as the junction voltages and the carrier distribution in different regions of the device, can be obtained using the models. Table of Contents: Introduction to Power Semiconductor Device Modeling/Physics of Power Semiconductor Devices/Modeling of a Power Diode and IGBT/IGBT Under an Inductive Load-Switching Condition in Simulink/Parameter Extraction. © 2013 by Morgan & Claypool.

Evolution of Wurtzite Structured GaAs Shells Around InAs Nanowire Cores.

GaAs was radially deposited on InAs nanowires by metal-organic chemical vapor deposition and resultant nanowire heterostructures were characterized by detailed electron microscopy investigations. The GaAs shells have been grown in wurtzite structure, epitaxially on the wurtzite structured InAs nanowire cores. The fundamental reason of structural evolution in terms of material nucleation and interfacial structure is given.