MOS and bipolar gated thyristor: A thyristor with IGBT switching characteristics

The IGBT has become the device of choice in many high-voltage-power electronic applications, by virtue of combining the ease of MOS gate control with an acceptable forward voltage drop. However, designers have retained an interest in MOS gated thyristor structures which have a turn-off capability. These offer low on-state losses as a result of their latching behaviour. Recently, there have been various proposals for dual-gate devices that have a thyristor on-state with IGBT-like switching. Many of these dual gated structures rely on advanced MOS technology, with inherent manufacturing difficulties. The MOS and bipolar gated thyristor offers all the advantages of dual gated performance, while employing standard IGBT processing techniques. The paper describes the MBGT in detail, and presents experimental and simulation results for devices based on realistic commercial processes. It is shown that the MBGT represents a viable power semiconductor device technology, suitable for a diverse range of applications. © IEE, 1998.

Switching speed enhancement of the LDMOSFETs using partial-SOI technology

To overcome reduced breakdown voltage and self-heating effects inherent in silicon-on-insulator (SOI) power integrated circuits while still maintaining good isolation between low power CMOS circuits and the high power cells, partial SOI (PSOI) technology has been proposed. PSOI devices make use of both buried oxide and substrate depletion to support the breakdown voltage. 2D analyses and modeling of parasitic capacitances in PSOI structures show that PSOI-lightly doped MOSFETs can increase the switching speed by as much as four times compared to conventional SOI structures, making them very attractive for high switching applications.

A new low-power highly linear mixer design using differential derivative superposition

This paper presents the analysis and design of a new low power and highly linear mixer topology based on a newly reported differential derivative superposition method. Volterra series and harmonic balance are employed to investigate its linearisation mechanism and to optimise the design. A prototype mixer has been designed and is being implemented in 0.18μm CMOS technology. Simulation shows this mixer achieves 19.7dBm IIP3 with 10.5dB conversion gain, 13.2dB noise figure at 2.4GHz and only 3.8mW power consumption. This performance is competitive with already reported mixers.

Spice modelling of the superjunction IGBT

This paper presents a SPICE model of the SuperJunction Insulated Gate Bipolar Transistor (SJIGBT) [1]. SPICE simulation results are in good agreement with the DESSIS simulation results under DC conditions. This model consists of an intrinsic MOSFET and a parallel combination of a wide and a narrow base pnp BJTs. A parasitic JFET is also included to account for the restricted current flow between two adjacent p-wells. In addition the JFET component also models the additional depletion region caused by the transverse junction at the upper side of the n-drift region where the current is mainly transported via majority carriers.

Carbon nanotube based cathodes for microwave amplifiers

We have studied two different kinds of electron tubes using a cold field emission cathode as the electron source. This cathode is an array of vertically aligned multiwall carbon nanotubes. The first device is a triode. With this device, we demonstrated the modulation at 32 GHZ of a 1.4 A/cm2 peak current density with a 82% modulation ratio. The second device is a traveling wave tube. For this device, the objective is to test a cathode delivering a 2 A/cm 2 electron beam. ©2009 IEEE.

Self-aligned high-resolution printed polymer transistors

A process to fabricate solution-processable thin-film transistors (TFTs) with a one-step self-aligned definition of the dimensions in all functional layers is demonstrated. The TFT-channel, semiconductor materials, and effective gate dimention of different layers are determined by a one-step imprint process and the subsequent pattern transfer without the need for multiple patterning and mask alignment. The process is compatible with fabrication of large-scale circuits. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Amorphous silicon display backplanes on plastic substrates

Amorphous silicon thin-film transistors and pixel driver circuits for organic light-emitting diode displays have been fabricated on plastic substrates. Pixel circuits demonstrate sufficient current delivery and long-term stable operation. © 2005 IEEE.

Channels that heat up

This paper considers an additive noise channel where the time-κ noise variance is a weighted sum of the squared magnitudes of the previous channel inputs plus a constant. This channel model accounts for the dependence of the intrinsic thermal noise on the data due to the heat dissipation associated with the transmission of data in electronic circuits: the data determine the transmitted signal, which in turn heats up the circuit and thus influences the power of the thermal noise. The capacity of this channel (both with and without feedback) is studied at low transmit powers and at high transmit powers. At low transmit powers, the slope of the capacity-versus-power curve at zero is computed and it is shown that the heating-up effect is beneficial. At high transmit powers, conditions are determined under which the capacity is bounded, i.e., under which the capacity does not grow to infinity as the allowed average power tends to infinity. © 2009 IEEE.

Low temperature (< 100 °c) deposited P-type cuprous oxide thin films: Importance of controlled oxygen and deposition energy

With the emergence of transparent electronics, there has been considerable advancement in n-type transparent semiconducting oxide (TSO) materials, such as ZnO, InGaZnO, and InSnO. Comparatively, the availability of p-type TSO materials is more scarce and the available materials are less mature. The development of p-type semiconductors is one of the key technologies needed to push transparent electronics and systems to the next frontier, particularly for implementing p-n junctions for solar cells and p-type transistors for complementary logic/circuits applications. Cuprous oxide (Cu2O) is one of the most promising candidates for p-type TSO materials. This paper reports the deposition of Cu2O thin films without substrate heating using a high deposition rate reactive sputtering technique, called high target utilisation sputtering (HiTUS). This technique allows independent control of the remote plasma density and the ion energy, thus providing finer control of the film properties and microstructure as well as reducing film stress. The effect of deposition parameters, including oxygen flow rate, plasma power and target power, on the properties of Cu2O films are reported. It is known from previously published work that the formation of pure Cu2O film is often difficult, due to the more ready formation or co-formation of cupric oxide (CuO). From our investigation, we established two key concurrent criteria needed for attaining Cu2O thin films (as opposed to CuO or mixed phase CuO/Cu2O films). First, the oxygen flow rate must be kept low to avoid over-oxidation of Cu2O to CuO and to ensure a non-oxidised/non-poisoned metallic copper target in the reactive sputtering environment. Secondly, the energy of the sputtered copper species must be kept low as higher reaction energy tends to favour the formation of CuO. The unique design of the HiTUS system enables the provision of a high density of low energy sputtered copper radicals/ions, and when combined with a controlled amount of oxygen, can produce good quality p-type transparent Cu2O films with electrical resistivity ranging from 102 to 104 Ω-cm, hole mobility of 1-10 cm2/V-s, and optical band-gap of 2.0-2.6 eV. These material properties make this low temperature deposited HiTUS Cu 2O film suitable for fabrication of p-type metal oxide thin film transistors. Furthermore, the capability to deposit Cu2O films with low film stress at low temperatures on plastic substrates renders this approach favourable for fabrication of flexible p-n junction solar cells. © 2011 Elsevier B.V. All rights reserved.

Derivation of a vector model for a Brushless Doubly-Fed Machine with multiple loops per nest

The paper presents a vector model for a Brushless Doubly-Fed Machine (BDFM). The BDFM has 4 and 8 pole stator windings and a nested-loop rotor cage. The rotor cage has six nests equally spaced around the circumference and each nest comprises three loops. All the rotor loops are short circuited via a common end-ring at one end. The vector model is derived based on the electrical equations of the machine and appropriate vector transformations. In contrast to the stator, there is no three phase circuit in the rotor. Therefore, the vector transformations suitable for three phase circuits can not be utilised for the rotor circuit. A new vector transformation is employed for the rotor circuit quantities. The approach presented in this paper can be extended for a BDFM with any stator poles combination and any number of loops per nest. Simulation results from the model implemented in Simulink are presented. © 2008 IEEE.

Integrated avalanche diode for 600 v Trench IGBT over-voltage protection

Avalanche multiplication has been one of the major destructive failure mechanisms in IGBTs; in order to avoid operating an IGBT under abnormal conditions, it is desirable to develop peripheral protecting circuits monolithically integrated without compromising the operation and performance of the IGBT. In this paper, a monolithically integrated avalanche diode (D av) for 600V Trench IGBT over-voltage protection is proposed. The mix-mode transient simulation proves the clamping capability of the D av when the IGBT is experiencing over-voltage stress in unclamped inductive switching (UIS) test. The spread of avalanche energy, which prevents hot-spot formation, through the help of the avalanche diode feeding back a large fraction of the avalanche current to a gate resistance (R G) is also explained. © 2011 IEEE.

A 4 GHz non-resonant clock driver with inductor-assisted energy return to power grid

Power consumption of a multi-GHz local clock driver is reduced by returning energy stored in the clock-tree load capacitance back to the on-chip power-distribution grid. We call this type of return energy recycling. To achieve a nearly square clock waveform, the energy is transferred in a non-resonant way using an on-chip inductor in a configuration resembling a full-bridge DC-DC converter. A zero-voltage switching technique is implemented in the clock driver to reduce dynamic power loss associated with the high switching frequencies. A prototype implemented in 90 nm CMOS shows a power savings of 35% at 4 GHz. The area needed for the inductor in this new clock driver is about 6% of a local clock region. © 2006 IEEE.

Growth of ultrahigh density single-walled carbon nanotube forests by improved catalyst design.

We have grown vertically aligned single-walled carbon nanotube forests with an area density of 1.5 × 10(13) cm(-2), the highest yet achieved, by reducing the average diameter of the nanotubes. We use a nanolaminate Fe-Al(2)O(3) catalyst design consisting of three layers of Al(2)O(3), Fe, and Al(2)O(3), in which the lower Al(2)O(3) layer is densified by an oxygen plasma treatment to increase its diffusion barrier properties, to allow a thinner catalyst layer to be used. This high nanotube density is desirable for using carbon nanotubes as interconnects in integrated circuits.