148 resultados para CMOS
Resumo:
We demonstrated the nonvolatile memory functionality of ZnO nanowire field effect transistors (FETs) using mobile protons that are generated by high-pressure hydrogen annealing (HPHA) at relatively low temperature (400 °C). These ZnO nanowire devices exhibited reproducible hysteresis, reversible switching, and nonvolatile memory behaviors in comparison with those of the conventional FET devices. We show that the memory characteristics are attributed to the movement of protons between the Si/SiO(2) interface and the SiO(2)/ZnO nanowire interface by the applied gate electric field. The memory mechanism is explained in terms of the tuning of interface properties, such as effective electric field, surface charge density, and surface barrier potential due to the movement of protons in the SiO(2) layer, consistent with the UV photoresponse characteristics of nanowire memory devices. Our study will further provide a useful route of creating memory functionality and incorporating proton-based storage elements onto a modified CMOS platform for FET memory devices using nanomaterials.
Resumo:
Rapid and effective thermal processing methods using electron beams are described in this paper. Heating times ranging from a fraction of a second to several seconds and temperatures up to 1400°C are attainable. Applications such as the annealing of ion implanted material, both without significant dopant diffusion and with highly controlled diffusion of impurities, are described. The technique has been used successfully to activate source/drain regions for fine geometry NMOS transistors. It is shown that electron beams can produce localised heating of semiconductor substrates and a resolution of approximately 1 μm has been achieved. Electron beam heating has been applied to improving the crystalline quality of silicon-on sapphire used in CMOS device fabrication. Silicon layers with defect levels approaching bulk material have been obtained. Finally, the combination of isothermal and selective annealing is shown to have application in recrystallisation of polysilicon films on an insulating layer. The approach provides the opportunity of producing a silicon-on-insulator substrate with improved crystalline quality compared to silicon-on-sapphire at a potentially lower cost. It is suggested that rapid heating methods are expected to provide a real alternative to conventional furnace processing of semiconductor devices in the development of fabrication technology. © 1984 Benn electronics Publications Ltd, Luton.
Resumo:
A novel CMOS-compatible, heavily doped drift auxiliary cathode lateral insulated gate transistor (HDD-ACLIGT) structure is analyzed using two-dimensional device simulation techniques. Simulation results indicate that low on-resistance and a fast turn-off time of less than 50 ns can be achieved by incorporating an additional n+ region which is self-aligned to the gate between the p+ auxiliary cathode and the p well, together with an extended p buried layer in an anode-shorted modified lateral insulated gate transistor (MLIGT) structure. The on-state and its transient performance are analyzed in detail. The on-state performances of the HDD-ACLIGT and the MLIGT are compared and discussed. The results indicate that the HDD-ACLIGT structure is well suited for HVICs. The device is also well suited for integration with self-aligned digital CMOS.
Resumo:
A high voltage integrated circuit (HVIC) switch designed as a building block for power converters operating up to 13.56 MHz from off-line voltages is presented. A CMOS-compatible, 500 V power device process is used to integrate control circuitry with a high-speed MOS gate driver and high voltage lateral power MOSFET. Fabrication of the HVIC switches has proceeded in two stages. The first batch of devices showed switching times of less than 5 ns for the power switch and good high frequency performance of a level-shifter for driving half bridge converters. In the second phase, a switch that monolithically integrates all the elements required to form a complete high-frequency converter has been designed.
Resumo:
To overcome reduced breakdown voltage and self-heating effects inherent in silicon-on-insulator (SOI) power integrated circuits while still maintaining good isolation between low power CMOS circuits and the high power cells, partial SOI (PSOI) technology has been proposed. PSOI devices make use of both buried oxide and substrate depletion to support the breakdown voltage. 2D analyses and modeling of parasitic capacitances in PSOI structures show that PSOI-lightly doped MOSFETs can increase the switching speed by as much as four times compared to conventional SOI structures, making them very attractive for high switching applications.
Resumo:
This paper presents the analysis and design of a new low power and highly linear mixer topology based on a newly reported differential derivative superposition method. Volterra series and harmonic balance are employed to investigate its linearisation mechanism and to optimise the design. A prototype mixer has been designed and is being implemented in 0.18μm CMOS technology. Simulation shows this mixer achieves 19.7dBm IIP3 with 10.5dB conversion gain, 13.2dB noise figure at 2.4GHz and only 3.8mW power consumption. This performance is competitive with already reported mixers.
Resumo:
CMOS nanocrystalline silicon thin film transistors with high field effect mobility are reported. The transistors were directly deposited by radio-frequency plasma enhanced chemical vapor deposition at 150°C The transistors show maximum field effect mobility of 450 cm2/V-s for electrons and 100 cm2/V-s for holes at room temperature. We attribute the high mobilities to a reduction of the oxygen content, which acts as an accidental donor. Indeed, secondary ion mass spectrometry measurements show that the impurity concentration in the nanocrystalline Si layer is comparable to, or lower than, the defect density in the material, which is already low thanks to hydrogen passivation.
Resumo:
This paper investigates the performance of diode temperature sensors when operated at ultra high temperatures (above 250°C). A low leakage Silicon On Insulator (SOI) diode was designed and fabricated in a 1 μm CMOS process and suspended within a dielectric membrane for efficient thermal insulation. The diode can be used for accurate temperature monitoring in a variety of sensors such as microcalorimeters, IR detectors, or thermal flow sensors. A CMOS compatible micro-heater was integrated with the diode for local heating. It was found that the diode forward voltage exhibited a linear dependence on temperature as long as the reverse saturation current remained below the forward driving current. We have proven experimentally that the maximum temperature can be as high as 550°C. Long term continuous operation at high temperatures (400°C) showed good stability of the voltage drop. Furthermore, we carried out a detailed theoretical analysis to determine the maximum operating temperature and exlain the presence of nonlinearity factors at ultra high temperatures. © 2008 IEEE.
Resumo:
As a novel implementation of the static random access memory (SRAM), the tunneling SRAM (TSRAM) uses the negative differential resistance of tunnel diodes (TD’s) and potentially offers considerable improvements in both standby power dissipation and integration density compared to the conventional CMOS SRAM. TSRAM has not yet been realized with a useful bit capacity mainly because the level of uniformity required of the nanoscale TD’s has been demanding and difficult to achieve. In this letter, we propose a Monte Carlo approach for estimating the yield of TSRAM cells and show that by optimizing the cell’s external circuit parameters, we can relax the allowable tolerance of a key device parameter of a resonant-TD-(RTD) based cell by three times.
Resumo:
Rapid thermal annealing of arsenic and boron difluoride implants, such as those used for source/drain regions in CMOS, has been carried out using a scanning electron beam annealer, as part of a study of transient diffusion effects. Three types of e-beam anneal have been performed, with peak temperatures in the range 900 -1200 degree C; the normal isothermal e-beam anneals, together with sub-second fast anneals and 'dual-pulse' anneals, in which the sample undergoes an isothermal pre-anneal followed by rapid heating to the required anneal temperature is less than 0. 5s. The diffusion occuring during these anneal cycles has been modelled using SPS-1D, an implant and diffusion modelling program developed by one of the authors. This has been modified to incorporate simulated temperature vs. time cycles for the anneals. Results are presented applying the usual equilibrium clustering model, a transient point-defect enhancement to the diffusivity proposed recently by Fair and a new dynamic clustering model for arsenic. Good agreement with SIMS measurements is obtained using the dynamic clustering model, without recourse to a transient defect model.
Resumo:
This paper advocates 'reduce, reuse, recycle' as a complete energy savings strategy. While reduction has been common to date, there is growing need to emphasize reuse and recycling as well. We design a DC-DC buck converter to demonstrate the 3 techniques: reduce with low-swing and zero voltage switching (ZVS), reuse with supply stacking, and recycle with regulated delivery of excess energy to the output load. The efficiency gained from these 3 techniques helps offset the loss of operating drivers at very high switching frequencies which are needed to move the output filter completely on-chip. A prototype was fabricated in 0.18μm CMOS, operates at 660MHz, and converts 2.2V to 0.75-1.0V at ∼50mA.1 © 2008 IEEE.
Resumo:
Power consumption of a multi-GHz local clock driver is reduced by returning energy stored in the clock-tree load capacitance back to the on-chip power-distribution grid. We call this type of return energy recycling. To achieve a nearly square clock waveform, the energy is transferred in a non-resonant way using an on-chip inductor in a configuration resembling a full-bridge DC-DC converter. A zero-voltage switching technique is implemented in the clock driver to reduce dynamic power loss associated with the high switching frequencies. A prototype implemented in 90 nm CMOS shows a power savings of 35% at 4 GHz. The area needed for the inductor in this new clock driver is about 6% of a local clock region. © 2006 IEEE.
Resumo:
In this paper we present a robust SOI-CMOS ethanol sensor based on a tungsten-doped lanthanum iron oxide sensing material. The device shows response to gas, has low power consumption, good uniformity, high temperature stability and can be manufactured at low cost and with integrated circuitry. The platform is a tungsten-based CMOS micro-hotplate that has been shown to be stable for over two thousand hours at a high temperature (600°C) in a form of accelerated life test. The tungsten-doped lanthanum iron oxide was deposited on the micro-hotplate as a slurry with terpineol using a syringe, dried and annealed. Preliminary gas testing was done and the material shows response to ethanol vapour. These results are promising and we believe that this combination of a robust CMOS micro-hotplate and a good sensing material can form the basis for a commercial CMOS gas sensor. © 2011 Published by Elsevier Ltd.
Resumo:
We have for the first time developed a self-aligned metal catalyst formation process using fully CMOS (complementary metal-oxide-semiconductor) compatible materials and techniques, for the synthesis of aligned carbon nanotubes (CNTs). By employing an electrically conductive cobalt disilicide (CoSi 2) layer as the starting material, a reactive ion etch (RIE) treatment and a hydrogen reduction step are used to transform the CoSi 2 surface into cobalt (Co) nanoparticles that are active to catalyze aligned CNT growth. Ohmic contacts between the conductive substrate and the CNTs are obtained. The process developed in this study can be applied to form metal nanoparticles in regions that cannot be patterned using conventional catalyst deposition methods, for example at the bottom of deep holes or on vertical surfaces. This catalyst formation method is crucially important for the fabrication of vertical and horizontal interconnect devices based on CNTs. © 2012 American Institute of Physics.
Resumo:
A bottom-up technique for synthesizing transversely suspended zinc oxide nanowires (ZnO NWs) under a zinc nitrate (Zn(NO 3) 2· 6H 2O) and hexamethylenetetramine (HMTA, (CH 2) 6·N 4) solution within a microfabricated device is reported in this paper. The device consists of a microheater which is used to initially create an oxidized ZnO seed layer. ZnO NWs are then locally synthesized by the microheater and electrodes embedded within the devices are used to drive electric field directed horizontal alignment of the nanowires within the device. The entire process is carried out at low temperature. This approach has the potential to considerably simplify the fabrication and assembly of ZnO nanowires on CMOS compatible substrates, allowing for the chemical synthesis to be carried out under near-ambient conditions by locally defining the conditions for nanowire growth on a silicon reactor chip. © 2012 IEEE.