126 resultados para Unbalanced Circuits


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Superconductors have a bright future; they are able to carry very high current densities, switch rapidly in electronic circuits, detect extremely small perturbations in magnetic fields, and sustain very high magnetic fields. Of most interest to large-scale electrical engineering applications are the ability to carry large currents and to provide large magnetic fields. There are many projects that use the first property, and these have concentrated on power generation, transmission, and utilization; however, there are relatively few, which are currently exploiting the ability to sustain high magnetic fields. The main reason for this is that high field wound magnets can and have been made from both BSCCO and YBCO, but currently, their cost is much higher than the alternative provided by low-Tc materials such as Nb3Sn and NbTi. An alternative form of the material is the bulk form, which can be magnetized to high fields. This paper explains the mechanism, which allows superconductors to be magnetized without the need for high field magnets to perform magnetization. A finite-element model is presented, which is based on the E-J current law. Results from this model show how magnetization of the superconductor builds up cycle upon cycle when a traveling magnetic wave is induced above the superconductor. © 2011 IEEE.

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With series insulated-gate bipolar transistor (IGBT) operation, well-matched gate drives will not ensure balanced dynamic voltage sharing between the switching devices. Rather, it is IGBT parasitic capacitances, mainly gate-to-collector capacitance Cgc, that dominate transient voltage sharing. As Cgc is collector voltage dependant and is significantly larger during the initial turn-off transition, it dominates IGBT dynamic voltage sharing. This paper presents an active control technique for series-connected IGBTs that allows their dynamic voltage transition dV\ce/dt to adaptively vary. Both switch ON and OFF transitions are controlled to follow a predefined dVce/dt. Switching losses associated with this technique are minimized by the adaptive dv /dt control technique incorporated into the design. A detailed description of the control circuits is presented in this paper. Experimental results with up to three series devices in a single-ended dc chopper circuit, operating at various low voltage and current levels, are used to illustrate the performance of the proposed technique. © 2012 IEEE.

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Through silicon via (TSV) technology is key for next generation three-dimensional integrated circuits, and carbon nanotubes (CNT) provide a promising alternative to metal for filling the TSV. Three catalyst preparation methods for achieving CNT growth from the bottom of the TSV are investigated. Compared with sputtering and evaporation, catalyst deposition using dip-coating in a FeCl2 solution is found to be a more efficient method for realizing a bottom-up filling of the TSV (aspect ratio 5 or 10) with CNT. The CNT bundles grown in 5 min exceed the 50 μm length of the TSV and are multi-wall CNT with three to eight walls. The CNT bundles inside the TSV were electrically characterized by creating a direct contact using a four-point nanoprober setup. A low resistance of the CNT bundle of 69.7 Ω (297 Ω) was measured when the CNT bundle was contacted midway along (over the full length of) the 25 μm deep TSV. The electrical characterization in combination with the good filling of the TSV demonstrates the potential use of CNT in fully integrated TSV applications.

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Large digital chips use a significant amount of energy to broadcast a low-skew, multigigahertz clock to millions of latches located throughout the chip. Every clock cycle, the large aggregate capacitance of the clock network is charged from the supply and then discharged to ground. Instead of wasting this stored energy, it is possible to recycle the energy by controlling its delivery to another part of the chip using an on-chip dc-dc converter. The clock driver and switching converter circuits share many compatible characteristics that allow them to be merged into a single design and fully integrated on-chip. Our buck converter prototype, manufactured in 90-nm CMOS, provides a proof-of-concept that clock network energy can be recycled to other parts of the chip, thus lowering overall energy consumption. It also confirms that monolithic multigigahertz switching converters utilizing zero-voltage switching can be implemented in deep-submicrometer CMOS. With multigigahertz operation, fully integrated inductors and capacitors use a small amount of chip area with low losses. Combining the clock driver with the power converter can share the large MOSFET drivers necessary as well as being energy and space efficient. We present an analysis of the losses which we confirm by experimentally comparing the merged circuit with a conventional clock driver. © 2012 IEEE.

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We demonstrate the fabrication of horizontally aligned carbon nanotube (HA-CNT) networks by spatially programmable folding, which is induced by self-directed liquid infiltration of vertical CNTs. Folding is caused by a capillary buckling instability and is predicted by the elastocapillary buckling height, which scales with the wall thickness as t(3/2). The folding direction is controlled by incorporating folding initiators at the ends of the CNT walls, and the initiators cause a tilt during densification which precedes buckling. By patterning these initiators and specifying the wall geometry, we control the dimensions of HA-CNT patches over 2 orders of magnitude and realize multilayered and multidirectional assemblies. Multidirectional HA-CNT patterns are building blocks for custom design of nanotextured surfaces and flexible circuits.

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The article discusses the progress and issues related to transparent oxide semiconductor (TOS) TFTs for advanced display and imaging applications. Amorphous oxide semiconductors continue to spark new technological developments in transparent electronics on a multitude of non-conventional substrates. Applications range from high-frame-rate interactive displays with embedded imaging to flexible electronics, where speed and transparency are essential requirements. TOS TFTs exhibit high transparency as well as high electron mobility even when fabricated at room temperature. Compared to conventional a-Si TFT technology, TOS TFTs have higher mobility and sufficiently good uniformity over large areas, similar in many ways to LTPS TFTs. Moreover, because the amorphous oxide semiconductor has higher mobility compared to that of conventional a-Si TFT technology, this allows higher-frame-rate display operation. This would greatly benefit OLED displays in particular because of the need for lower-cost higher-mobility analog circuits at every subpixel.

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Graphene is a single layer of covalently bonded carbon atoms, which was discovered only 8 years ago and yet has already attracted intense research and commercial interest. Initial research focused on its remarkable electronic properties, such as the observation of massless Dirac fermions and the half-integer quantum Hall effect. Now graphene is finding application in touch-screen displays, as channels in high-frequency transistors and in graphene-based integrated circuits. The potential for using the unique properties of graphene in terahertz-frequency electronics is particularly exciting; however, initial experiments probing the terahertz-frequency response of graphene are only just emerging. Here we show that the photoconductivity of graphene at terahertz frequencies is dramatically altered by the adsorption of atmospheric gases, such as nitrogen and oxygen. Furthermore, we observe the signature of terahertz stimulated emission from gas-adsorbed graphene. Our findings highlight the importance of environmental conditions on the design and fabrication of high-speed, graphene-based devices.

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While the plasticity of excitatory synaptic connections in the brain has been widely studied, the plasticity of inhibitory connections is much less understood. Here, we present recent experimental and theoretical □ndings concerning the rules of spike timing-dependent inhibitory plasticity and their putative network function. This is a summary of a workshop at the COSYNE conference 2012.

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Multimode polymer waveguides are promising for use in board-level optical interconnects. In recent years, various on-board optical interconnection architectures have been demonstrated making use of passive routing waveguide components. In particular, 90° bends have played important roles in complex waveguide layouts enabling interconnection between non co-linear points on a board. Due to the dimensions and index step of the waveguides typically used in on-board optical interconnects, low-loss bends are typically limited to a radius of ∼ 10 mm. This paper therefore presents the design and fabrication of compact low-loss waveguide bends with reduced radii of curvature, offering significant reductions in the required areas for on-board optical circuits. The proposed design relies on the exposure of the bend section to the air, achieving tighter light confinement along the bend and reduced bending losses. Simulation studies carried out with ray tracing tools and experimental results from polymer samples fabricated on FR4 are presented. Low bending losses are achieved from the air-exposed bends up to 4 mm of radius of curvature, while an improvement of 14 μm in the 1 dB alignment tolerances at the input of these devices (fibre to waveguide coupling) is also obtained. Finally, the air-exposed bends are employed in an optical bus structure, offering reductions in insertion loss of up to 3.8 dB. © 2013 IEEE.

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IGBTs realise high-performance power converters. Unfortunately, with fast switching of the IGBT-free wheel diode chopper cell, such circuits are intrinsic sources of high-level EMI. Therefore, costly EMI filters or shielding are normally needed on the load and supply side. In order to design these EMI suppression components, designers need to predict the EMI level with reasonable accuracy for a given structure and operating mode. Simplifying the transient IGBT switching current and voltage into a multiple slope switching waveform approximation offers a feasible way to estimate conducted EMI with some accuracy. This method is dependent on the availability of high-fidelity measurements. Also, that multiple slope approximation needs careful and time-costly IGBT parameters optimisation process to approach the real switching waveform. In this paper, Active Voltage Control Gate Drive(AVC GD) is employed to shape IGBT switching into several defined slopes. As a result, Conducted EMI prediction by multiple slope switching approximation could be more accurate, less costly but more friendly for implementation. © 2013 IEEE.

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Thyristors are usually three-terminal devices that have four layers of alternating p-type and n-type material (i.e. three p-n junctions) comprising its main power handling section. In contrast to the linear relation which exists between load and control currents in a transistor, the thyristor is bistable. The control terminal of the thyristor, called the gate (G) electrode, may be connected to an integrated and complex structure as a part of the device. Thyristors are used to approximate ideal closed (no voltage drop between anode and cathode) or open (no anode current flow) switches for control of power flow in a circuit. This differs from low-level digital switching circuits that are designed to deliver two distinct small voltage levels while conducting small currents (ideally zero). Thyristor circuits must have the capability of delivering large currents and be able to withstand large externally applied voltages. All thyristor types are controllable in switching from a forward-lockingstate (positive potential applied to the anode with respect to the cathode, with correspondingly little anode current flow) into a forward-conduction state (large forward anode current flowing, with a small anode-cathode potential drop). Most thyristors have the characteristic that after switching from a forward-blocking state into the forward-conduction state, the gate signal can be removed and the thyristor will remain in its forward-conduction mode. This property is termed "latching" and is an important distinction between thyristors and other types of power electronic devices. © 2007 Elsevier Inc. All rights reserved.

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Nowadays, all new wind turbine generators have to meet strict grid codes, especially riding through certain grid faults, such as a low voltage caused by grid short circuits. The Low-Voltage Ride Through (LVRT) capability has become a key issue in assessing the performance of wind turbine generators. The mediumspeed Brushless DFIG in combination with a simplified two-stage gearbox shows commercial promise as a replacement for conventional DFIGs due to its lower cost and higher reliability. Furthermore, the Brushless DFIG has significantly improved LVRT performance when compared with the DFIG due to its inherent design characteristics. In this paper, the authors propose a control strategy for the Brushless DFIG to improve its LVRT performance. The controller has been implemented on a prototype 250 kW Brushless DFIG and test results show that LVRT is possible without a need for any external protective hardware such as a crowbar.

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Brushless doubly fed induction generator (BDFIG) has substantial benefits, which make it an attractive alternative as a wind turbine generator. However, it suffers from lower efficiency and larger dimensions in comparison to DFIG. Hence, optimizing the BDFIG structure is necessary for enhancing its situation commercially. In previous studies, a simple model has been used in BDFIG design procedure that is insufficiently accurate. Furthermore, magnetic saturation and iron loss are not considered because of difficulties in determination of flux density distributions. The aim of this paper is to establish an accurate yet computationally fast model suitable for BDFIG design studies. The proposed approach combines three equivalent circuits including electric, magnetic and thermal models. Utilizing electric equivalent circuit makes it possible to apply static form of magnetic equivalent circuit, because the elapsed time to reach steady-state results in the dynamic form is too long for using in population-based design studies. The operating characteristics, which are necessary for evaluating the objective function and constraints values of the optimization problem, can be calculated using the presented approach considering iron loss, saturation, and geometrical details. The simulation results of a D-180 prototype BDFIG are compared with measured data in order to validate the developed model. © 1986-2012 IEEE.

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Despite material weaknesses, considerable progress has been made in designing large area systems such as displays and imaging arrays. This talk will address the various large area technologies, and in particular, review amorphous oxide semiconductors and associated design approaches, along with driving schemes for displays, imaging and other applications. © 2013 IEEE.

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We demonstrate the design, fabrication, transmission spectrum measurement, and near-field characterization of a parabolic tapered one-dimensional photonic crystal cavity in silicon. The results shows a relatively high quality factor (∼43 000), together with a small modal volume of ∼ 1. 1 (λ/n) 3. Moreover, the design allows repeatable device fabrication, as evident by the similar characteristics obtained for several tens of devices that were fabricated and tested. These demonstrated 1D PhC cavities may be used as a building block in integrated photonic circuits for optical on-chip interconnects and sensing applications. © 2012 American Institute of Physics.