Switching speed enhancement of the LDMOSFETs using partial-SOI technology

To overcome reduced breakdown voltage and self-heating effects inherent in silicon-on-insulator (SOI) power integrated circuits while still maintaining good isolation between low power CMOS circuits and the high power cells, partial SOI (PSOI) technology has been proposed. PSOI devices make use of both buried oxide and substrate depletion to support the breakdown voltage. 2D analyses and modeling of parasitic capacitances in PSOI structures show that PSOI-lightly doped MOSFETs can increase the switching speed by as much as four times compared to conventional SOI structures, making them very attractive for high switching applications.

Carbon nanotube based photocathodes for high frequency amplifiers

The combination of high frequency, high power, high efficiency capabilities is a feature of vacuum tube technology. For most of applications, large bandwidths are required, and therefore the modulation method should also allow large bandwidth operation. Optically modulated cold cathodes, avoiding the use of resonant cavities, should satisfy this requirement. This is the reason why we have developed carbon nanotube based photocathode.© 2009 IEEE.

Progress in ultra-high modulation efficiency tapered lasers for free-space communications

Simultaneous high power (2W), high modulation speed (1Gb/s) and high modulation efficiency (14 W/A) operation of a two-electrode tapered laser is reported. © 2011 IEEE.

FPGA, physics-based modeling of IGBT and pin diode for hardware co-simulation of complex power electronic converters and systems

This paper presents the steps and the challenges for implementing analytical, physics-based models for the insulated gate bipolar transistor (IGBT) and the PIN diode in hardware and more specifically in field programmable gate arrays (FPGAs). The models can be utilised in hardware co-simulation of complex power electronic converters and entire power systems in order to reduce the simulation time without compromising the accuracy of results. Such a co-simulation allows reliable prediction of the system's performance as well as accurate investigation of the power devices' behaviour during operation. Ultimately, this will allow application-specific optimisation of the devices' structure, circuit topologies as well as enhancement of the control and/or protection schemes.

Towards a fast electro-thermo-mechanical IGBT/Diode simulation framework for design of reliable power electronic converters

This paper describes a methodology that enables fast and reasonably accurate prediction of the reliability of power electronic modules featuring IGBTs and p-i-n diodes, by taking into account thermo-mechanical failure mechanisms of the devices and their associated packaging. In brief, the proposed simulation framework performs two main tasks which are tightly linked together: (i) the generation of the power devices' transient thermal response for realistic long load cycles and (ii) the prediction of the power modules' lifetime based on the obtained temperature profiles. In doing so the first task employs compact, physics-based device models, power losses lookup tables and polynomials and combined material-failure and thermal modelling, while the second task uses advanced reliability tests for failure mode and time-to-failure estimation. The proposed technique is intended to be utilised as a design/optimisation tool for reliable power electronic converters, since it allows easy and fast investigation of the effects that changes in circuit topology or devices' characteristics and packaging have on the reliability of the employed power electronic modules. © 2012 IEEE.

Superradiant emission in semiconductor diode laser structures

This paper reviews recent advances in superradiant (SR) emission in semiconductors at room temperature, a process which has been shown to enable the generation on demand of high power picosecond or subpicosecond pulses across a range of different wavelengths. The different characteristic features of SR emission from semiconductor devices with bulk, quantum-well, and quantum-dot active regions are outlined, and particular emphasis is placed on comparing the characteristic features of SR with those of lasing. Finally, potential applications of SR pulses are discussed. © 1995-2012 IEEE.

Comparison of square and hexagonal fuel lattices for high conversion PWRs

This paper reports on an investigation into fuel design choices of a pressurized water reactor operating in a self-sustainable Th- 233U fuel cycle. In order to evaluate feasibility of this concept, two types of fuel assembly lattices were considered: square and hexagonal. The hexagonal lattice may offer some advantages over the square one. For example, the fertile blanket fuel can be packed more tightly reducing the blanket volume fraction in the core and potentially allowing to achieve higher core average power density. The calculations were carried out with Monte-Carlo based BGCore code system and the results were compared to those obtained with Serpent Monte-Carlo code and deterministic transport code BOXER. One of the major design challenges associated with the SB concept is high power peaking due to the high concentration of fissile material in the seed region. The second objective of this work is to estimate the maximum achievable core power density by evaluation of limiting thermal hydraulic parameters. The analysis showed that both fuel assembly designs have a potential of achieving net breeding. Although hexagonal lattice was found to be somewhat more favorable because it allows achieving higher power density, while having breeding performance comparable to the square lattice case. © Carl Hanser Verlag München.

Gate commutated thyristor with voltage independent maximum controllable current

In this letter, we use a novel 3-D model, earlier calibrated with experimental results on standard gate commutated thyristors (GCTs), with the aim to explain the physics behind the high-power technology (HPT) GCT, to investigate what impact this design would have on 24 mm diameter GCTs, and to clarify the mechanisms that limit safe switching at different dc-link voltages. The 3-D simulation results show that the HPT design can increase the maximum controllable current in 24 mm diameter devices beyond the realm of GCT switching, known as the hard-drive limit. It is proposed that the maximum controllable current becomes independent of the dc-link voltage for the complete range of operating voltage. © 1980-2012 IEEE.

Use of vertically-aligned carbon nanotube array to enhance the performance of electrochemical capacitors

In the domain of energy storage, electrochemical capacitors have numerous applications ranging from hybrid vehicles to consumer electronics, with very high power density at the cost of relatively low energy storage. Here, we report an approach that uses vertically aligned carbon nanotube arrays as electrodes in electrochemical capacitors. Different electrolytes were used and multiple parameters of carbon nanotube array were compared: carbon nanotube arrays were shown to be two to three times better than graphite in term of specific capacitance, while the surface functionalization was demonstrated to be a critical factor in both aqueous and nonaqueous solutions to increase the specific capacitance. We found that a maximum energy density of 21 Wh/kg at a power density of 1.1 kW/kg for a hydrophilic electrode, could be easily achieved by using tetraethylammonium tetrafluoroborate in propylene carbonate. These are encouraging results in the path of energy-storage devices with both high energy density and power density, using only carbon-based materials for the electrodes with a very long lifetime, of tens of thousands of cycles. © 2011 IEEE.

On the variation of the 2DEG charge density with the density of the surface donor traps in AiGaN/GaN transistors

Gallium nitride (GaN) has a bright future in high voltage device owing to its remarkable physical properties and the possibility of growing heterostructures on silicon substrates. GaN High Electron Mobility Transistors (HEMTs) are expected to make a strong impact in off line applications and LED drives. However, unlike in silicon-based power devices, the on-state resistance of HEMT devices is hugely influenced by donor and acceptor traps at interfaces and in the bulk. This study focuses on the influence of donor traps located at the top interface between the semiconductor layer and the silicon nitride on the 2DEG density. It is shown through TCAD simulations and analytical study that the 2DEG charge density has an 'S' shape variation with two distinctive 'flat' regions, wherein it is not affected by the donor concentration, and one linear region. wherein the channel density increases proportionally with the donor concentration. We also show that the upper threshold value of the donor concentration within this 'S' shape increases significantly with the AIGaN thickness and the Al mole fraction and is highly affected by the presence of a thin GaN cap layer. © 2013 IEEE.

Fabrication of diamond based schottky barrier diodes with oxide ramp termination

The paper's goal is the first demonstration of the fabrication of high power Schottky diodes on synthetic diamond using oxide ramp termination. In order to allow full activated impurities at room temperature and a high hole mobility a low boron doping of the drift layer is employed. Several aspects of the manufacturing technology are presented. A termination with a small ramp angle can be obtained using only RIE technique due to diamond wafer nonuniformity (roughness). Experimental forward and reverse characteristics measured on diamond diodes are also included. © 2007 IEEE.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.