High-resolution TEM characterization of ZnO core-shell nanowires for dye-sensitized solar cells

Recently ZnO nanowire films have been used in very promising and inexpensive dye-sensitized solar cells (DSSC). It was found that the performance of the devices can be enhanced by functionalising the nanowires with a thin metal oxide coating. This nm-scale shell is believed to tailor the electronic structure of the nanowire, and help the absorption of the dye. Core-shell ZnO nanowire structures are synthesised at low temperature (below 120°C) by consecutive hydrothermal growth steps. Different materials are investigated for the coating, including Mg, Al, Cs and Zr oxides. High resolution TEM is used to characterise the quality of both the nanowire core and the shell, and to monitor the thickness and the degree of crystallisation of the oxide coating. The interface between the nanowire core and the outer shell is investigated in order to understand the adhesion of the coating, and give valuable feedback for the synthesis process. Nanowire films are packaged into dye-sensitised solar cell prototypes; samples coated with ZrO2 and MgO show the largest enhancement in the photocurrent and open-circuit voltage and look very promising for further improvement. © 2010 IOP Publishing Ltd.

A bulk acoustic mode single-crystal silicon microresonator with a high-quality factor

This paper details a bulk acoustic mode resonator fabricated in single-crystal silicon with a quality factor of 15 000 in air, and over a million below 10 mTorr at a resonant frequency of 2.18 MHz. The resonator is a square plate that is excited in the square-extensional mode and has been fabricated in a commercial foundry silicon-on-insulator (SOI) MEMS process through MEMSCAP. This paper also presents a simple method of extracting resonator parameters from raw measurements heavily buried in electrical feedthrough. Its accuracy has been demonstrated through a comparison between extracted motional resistance values measured at different voltage biases and those predicted from an analytical model. Finally, a method of substantially cancelling electrical feedthrough through system-level electronic implementation is also introduced. © 2008 IOP Publishing Ltd.

Binary excitation of a high-Q bulk acoustic microresonator by actuation polarity inversion

We present a technique for independently exciting two resonant modes of vibration in a single-crystal silicon bulk mode microresonator using the same electrode configuration through control of the polarity of the DC actuation voltage. Applications of this technique may include built-in temperature compensation by the simultaneous selective excitation of two closely spaced modes that may have different temperature coefficients of resonant frequency. The technique is simple and requires minimum circuit overhead for implementation. The technique is implemented on square plate resonators with quality factors as high as 3.06 × 106. Copyright © 2008 by ASME.

Advantages of top-gate, high-k dielectric carbon nanotube field-effect transistors

The subthreshold slope, transconductance, threshold voltage, and hysteresis of a carbon nanotube field-effect transistor (CNT FET) were examined as its configuration was changed from bottom-gate exposed channel, bottom-gate covered channel to top-gate FET. An individual single wall CNT was grown by chemical vapor deposition and its gate configuration was changed while determining its transistor characteristics to ensure that the measurements were not a function of different chirality or diameter CNTs. The bottom-gate exposed CNT FET utilized 900 nm SiO2 as the gate insulator. This CNT FET was then covered with TiO2 to form the bottom-gate covered channel CNT FET. Finally, the top-gate CNT FET was fabricated and the device utilized TiO 2 (K ∼ 80, equivalent oxide thickness=0.25 nm) as the gate insulator. Of the three configurations investigated, the top-gate device exhibited best subthreshold slope (67-70 mV/dec), highest transconductance (1.3 μS), and negligible hysteresis in terms of threshold voltage shift. © 2006 American Institute of Physics.

SOI diode temperature sensor operated at ultra high temperatures-a critical analysis

This paper investigates the performance of diode temperature sensors when operated at ultra high temperatures (above 250°C). A low leakage Silicon On Insulator (SOI) diode was designed and fabricated in a 1 μm CMOS process and suspended within a dielectric membrane for efficient thermal insulation. The diode can be used for accurate temperature monitoring in a variety of sensors such as microcalorimeters, IR detectors, or thermal flow sensors. A CMOS compatible micro-heater was integrated with the diode for local heating. It was found that the diode forward voltage exhibited a linear dependence on temperature as long as the reverse saturation current remained below the forward driving current. We have proven experimentally that the maximum temperature can be as high as 550°C. Long term continuous operation at high temperatures (400°C) showed good stability of the voltage drop. Furthermore, we carried out a detailed theoretical analysis to determine the maximum operating temperature and exlain the presence of nonlinearity factors at ultra high temperatures. © 2008 IEEE.

Energy recovery from high-frequency clocks using DC-DC converters

Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large capacitor is wasted. Instead, the energy can be recovered using an on-chip DC-DC converter. This paper investigates the integration of two DC-DC converter topologies, boost and buck-boost, with a high-speed clock driver. The high operating frequency significantly shrinks the required size of the L and C components so they can be placed on-chip; typical converters place them off-chip. The clock driver and DC-DC converter are able to share the entire tapered buffer chain, including the widest drive transistors in the final stage. To achieve voltage regulation, the clock duty cycle must be modulated; implying only single-edge-triggered flops should be used. However, this minor drawback is eclipsed by the benefits: by recovering energy from the clock, the output power can actually exceed the additional power needed to operate the converter circuitry, resulting in an effective efficiency greater than 100%. Furthermore, the converter output can be used to operate additional power-saving features like low-voltage islands or body bias voltages. ©2008 IEEE.

High velocity vortex channeling in vicinal YBCO thin films

We report on electrical transport measurements at high current densities on optimally doped YBa 2Cu 3O 7-δ thin films grown on vicinal SrTiO 3 substrates. Data were collected by using a pulsed-current technique in a four-probe arrangement, allowing to extend the current-voltage characteristics to high supercritical current densities (up to 24 MA cm -2) and high electric fields (more than 20 V/cm), in the superconducting state at temperatures between 30 and 80 K. The electric measurements were performed on tracks perpendicular to the vicinal step direction, such that the current crossed between ab planes, under magnetic field rotated in the plane defined by the crystallographic c axis and the current density. At magnetic field orientation parallel to the cuprate layers, evidence for the sliding motion along the ab planes (vortex channeling) was found. The signature of vortex channeling appeared to get enhanced with increasing electric field, due to the peculiar depinning features in the kinked vortex range. They give rise to a current-voltage characteristics steeper than in the more off-plane rectilinear vortex orientations, in the electric field range below approximately 1 V/cm. Roughly above this value, the high vortex channeling velocities (up to 8.6 km/s) could be ascribed to the flux flow, although the signature of ohmic transport appeared to be altered by unavoidable macroscopic self-heating and hot-electron-like effects. © 2012 Elsevier B.V. All rights reserved.

Breakdown voltage for superjunction power devices with charge imbalance: An analytical model valid for both punch through and non punch through devices

An analytical model for the electric field and the breakdown voltage (BV) of an unbalanced superjunction (SJ) device is presented in this paper. The analytical technique uses a superposition approach treating the asymmetric charge in the pillars as an excess charge component superimposed on a balanced charge component. The proposed double-exponentialmodel is able to accurately predict the electric field and the BV for unbalanced SJ devices in both punch through and non punch through conditions. The model is also reasonably accurate at extremely high levels of charge imbalance when the devices behave similarly to a PiN diode or to a high-conductance layer. The analytical model is compared against numerical simulations of charge unbalanced SJ devices and against experimental results. © 2009 IEEE.

Measurements and calculations of transport AC loss in second generation high temperature superconducting pancake coils

Theoretical and experimental AC loss data on a superconducting pancake coil wound using second generation (2 G) conductors are presented. An anisotropic critical state model is used to calculate critical current and the AC losses of a superconducting pancake coil. In the coil there are two regions, the critical state region and the subcritical region. The model assumes that in the subcritical region the flux lines are parallel to the tape wide face. AC losses of the superconducting pancake coil are calculated using this model. Both calorimetric and electrical techniques were used to measure AC losses in the coil. The calorimetric method is based on measuring the boil-off rate of liquid nitrogen. The electric method used a compensation circuit to eliminate the inductive component to measure the loss voltage of the coil. The experimental results are consistent with the theoretical calculations thus validating the anisotropic critical state model for loss estimations in the superconducting pancake coil. © 2011 American Institute of Physics.

Study of second generation, high-temperature superconducting coils: Determination of critical current

This paper presents the modeling of second generation (2 G) high-temperature superconducting (HTS) pancake coils using finite element method. The axial symmetric model can be used to calculate current and magnetic field distribution inside the coil. The anisotropic characteristics of 2 G tapes are included in the model by direct interpolation. The model is validated by comparing to experimental results. We use the model to study critical currents of 2 G coils and find that 100μV/m is too high a criterion to determine long-term operating current of the coils, because the innermost turns of a coil will, due to the effect of local magnetic field, reach their critical current much earlier than outer turns. Our modeling shows that an average voltage criterion of 20μV/m over the coil corresponds to the point at which the innermost turns' electric field exceeds 100μV/m. So 20μV/m is suggested to be the critical current criterion of the HTS coil. The influence of background field on the coil critical current is also studied in the paper. © 2012 American Institute of Physics.

Dual gate photo-thin film transistor with high photoconductive gain for high reliability, and low noise flat panel transparent imager

In this presentation, we report excellent electrical and optical characteristics of a dual gate photo thin film transistor (TFT) with bi-layer oxide channel, which was designed to provide virgin threshold voltage (V T) control, improve the negative bias illumination temperature stress (NBITS) reliability, and offer high photoconductive gain. In order to address the photo-sensitivity of phototransistor for the incoming light, top transparent InZnO (IZO) gate was employed, which enables the independent gate control of dual gate photo-TFT without having any degradation of its photosensitivity. Considering optimum initial V T and NBITS reliability for the device operation, the top gate bias was judiciously chosen. In addition, the speed and noise performance of the photo-TFT is competitive with silicon photo-transistors, and more importantly, its superiority lies in optical transparency. © 2011 IEEE.

A fast 600-V Tandem PiN Schottky (TPS) rectifier with ultra-low on-state voltage

The Tandem PiN Schottky (TPS) rectifier features lowly-doped p-layers in both active and termination regions, and is applied in 600-V rating for the first time. In the active region, the Schottky contact is in series connection with a transparent p-layer, leading to a superior forward performance than the conventional diodes. In addition, due to the benefit of moderate hole injection from the p-layer, the TPS offers a better trade-off between the on-state voltage and the switching speed. The active p-layer also helps to stabilise the Schottky contact, and hence the electrical data distributions are more concentrated. Regarding the floating p-layer in the termination region, its purpose is to reduce the peak electric fields, and the TPS demonstrates a high breakdown voltage with a compact termination width, less than 70% of the state-of-the-art devices on the market. Experimental results have shown that the 600-V TPS rectifier has an ultra-low on-state voltage of 0.98 V at 250 A/cm 2, a fast turn-off time of 75 ns by the standard RG1 test (I F=0.5A, I R=1A, and I RR=0.25A) and a breakdown voltage over 720 V. It is noteworthy that the p-layers in the active and termination regions can be formed at no extra cost for the use of self-alignment process. © 2012 IEEE.

High-precision digital lock-in measurements of critical current and AC loss in HTS 2G-Tapes

Application of High Temperature Superconducting (HTS) has been increasingly popular since the new superconducting materials were discovered. This paper presents a new high-precision digital lock-in measurement technique which is used for measuring critical current and AC loss of the 2nd Generation HTS tape. Using a lock-in amplifier and nano-voltage meter, we can resolve signals at nano-volt level, while using a specially designed compensation coil we can cancel out inductive by adjusting the coil inductance. Furthermore, a finer correction for the inductive component can be achieved by adjusting the reference phase of the lock-in amplifier. The critical current and AC loss measurement algorithms and hardware layout are described and analyzed, and results for both numerical and experimental data under varieties of frequencies are presented. © 2008 SICE.

SuperJunction IGBTS: An evolutionary step of silicon power devices with high impact potential

15 years ago the vertical SuperJunction (SJ) concept conceived for SJ power MOSFETs was the last, major breakthrough in the field of silicon power devices. Today, the SuperJunction MOSFET technologies have reached a mature stage characterized by gradual performance improvements. SuperJunction Insulated Gate Bipolar Transistors (SJ IGBTs) could interrupt this stagnation holding promise to revitalize voltage classes from 600 up to 1200 V. Such SJ IGBTs surpass by a very significant margin their SJ MOSFET counterparts both in terms of power handling capability, on-state and turn-off losses, all at the same time. On the higher end of the voltage class, SJ IGBTs would top the performance of 1.2 kV IGBTs by a similar margin. © 2012 IEEE.

Use of a high-temperature superconducting coil for magnetic energy storage

A high temperature superconducting magnetic energy storage device (SMES) has been realised using a 350 m-long BSCCO tape wound as a pancake coil. The coil is mounted on a cryocooler allowing temperatures down to 17.2 K to be achieved. The temperature dependence of coil electrical resistance R(T) shows a superconducting transition at T 102.5 K. Measurements of the V(I) characteristics were performed at several temperatures between 17.2 K and 101.5 K to obtain the temperature dependence of the critical current (using a 1 νV/cm criterion). Critical currents were found to exceed 100 A for T < 30 K. An electronic DC-DC converter was built in order to control the energy flow in and out of the superconducting coil. The converter consists of a MOS transistor bridge switching at a 80 kHz frequency and controlled with standard Pulse Width Modulation (PWM) techniques. The system was tested using a 30 V squared wave power supply as bridge input voltage. The coil current, the bridge input and output voltages were recorded simultaneously. Using a 10 A setpoint current in the superconducting coil, the whole system (coil + DC-DC converter) can provide a stable output voltage showing uninterruptible power supply (UPS) capabilities over 1 s. © 2006 IOP Publishing Ltd.