Computer-based selection of joining processes

The assembly of any manufactured product involves joining. This paper describes ways of selecting processes for joining. The method allows discrimination of the joint geometry, joint loading, material, and other attributes of the joint itself, identifying the subset of available processes capable of meeting a given set of design constraints. A relational database containing data-tables for joining processes, materials to be joined, and joint geometry and mode of loading, allows the attributes of each of these to be stored in an appropriate format, and permits links to be created between those that are related. A search engine isolates the processes that meet design requirements on material, joint geometry and loading. The method is illustrated in Part 2 by case studies, utilising software that embodies the method.

Performance optimization of adaptive loading algorithms for SMF-based optical OFDM transceivers

Detailed investigations of the effectiveness of three widely adopted optical orthogonal frequency division multiplexing (OOFDM) adaptive loading algorithms, including power loading (PL), bit loading (BL), and bit-and-power loading (BPL), are undertaken, over < 100km single-mode fibre (SMF) system without incorporating inline optical amplification and chromatic dispersion (CD) compensation. It is shown that the BPL (PL) algorithm always offers the best (worst) transmission performance. The absolute transmission capacity differences between these algorithms are independent of transmission distance and launched optical power. Moreover, it is shown that in comparison with the most sophisticated BPL algorithm, the simplest PL algorithm is effective in escalating the OOFDM SMF links performance to its maximum potential. On the other hand, when employing a large number of subcarriers and a high digital-to-analogue DAC)/analogue-to-digital (ADC) sampling rate, the sophisticated BPL algorithm has to be adopted. © 2011 IEEE.

Design and optimization of a 250nm SOI LDMOSFET

This work is aimed at optimising the static performance of a high voltage SOI LDMOSFET. Starting with a conventional LDMOSFET, 2D and 3D numerical simulation models, able to accurately match datasheet values, have been developed. Moving from the original device, several design techniques have been investigated with the target of improving the breakdown voltage and the ON-state resistance. The considered design techniques are based on the modification of the doping profile of the drift region and the Superjunction design technique. The paper shows that a single step doping within the drift region is the best design choice for the considered device and is found to give a 24% improvement in the breakdown voltage and a 17% reduction of the ON-state resistance. © 2011 IEEE.