Optimization of efficiency-loss figure of merit in carrier-depletion silicon Mach-Zehnder optical modulator.

In this paper we study the optimization of interleaved Mach-Zehnder silicon carrier depletion electro-optic modulator. Following the simulation results we demonstrate a phase shifter with the lowest figure of merit (modulation efficiency multiplied by the loss per unit length) 6.7 V-dB. This result was achieved by reducing the junction width to 200 nm along the phase-shifter and optimizing the doping levels of the PN junction for operation in nearly fully depleted mode. The demonstrated low FOM is the result of both low V(π)L of ~0.78 Vcm (at reverse bias of 1V), and low free carrier loss (~6.6 dB/cm for zero bias). Our simulation results indicate that additional improvement in performance may be achieved by further reducing the junction width followed by increasing the doping levels.

Highly efficient detector of the neurotransmitter ACh and AChE inhibitors

Among the variety of applications for biosensors one of the exciting frontiers is to utilize those devices as post-synaptic sensing elements in chemical coupling between neurons and solid-state systems. The first necessary step to attain this challenge is to realize highly efficient detector for neurotransmitter acetylcholine (ACh). Herein, we demonstrate that the combination of floating gate configuration of ion-sensitive field effect transistor (ISFET) together with diluted covalent anchoring of enzyme acetylcholinesterase (AChE) onto device sensing area reveals a remarkable improvement of a four orders of magnitude in dose response to ACh. This high range sensitivity in addition to the benefits of peculiar microelectronic design show, that the presented hybrid provides a competent platform for assembly of artificial chemical synapse junction. Furthermore, our system exhibits clear response to eserine, a competitive inhibitor of AChE, and therefore it can be implemented as an effective sensor of pharmacological reagents, organophosphates, and nerve gases as well. © 2007 Materials Research Society.

Optimising the dynamic performance of an all-wide-bandgap cascode switch

A SPICE simulation model of a novel cascode switch that combines a high voltage normally-on silicon carbide (SiC) junction field effect transistor (JFET) with a low voltage enhancement-mode gallium nitride field effect transistor (eGaN FET) has been developed, with the aim of optimising cascode switching performance. The effect of gate resistance on stability and switching losses is investigated and optimum values chosen. The effects of stray inductance on cascode switching performance are considered and the benefits of low inductance packaging discussed. The use of a positive JFET gate bias in a cascode switch is shown to reduce switching losses as well as reducing on-state losses. The findings of the simulation are used to produce a list of priorities for the design and layout of wide-bandgap cascode switches, relevant to both SiC and GaN high voltage devices. © 2013 IEEE.