Kernel conditional quantile estimation via reduction revisited

Quantile regression refers to the process of estimating the quantiles of a conditional distribution and has many important applications within econometrics and data mining, among other domains. In this paper, we show how to estimate these conditional quantile functions within a Bayes risk minimization framework using a Gaussian process prior. The resulting non-parametric probabilistic model is easy to implement and allows non-crossing quantile functions to be enforced. Moreover, it can directly be used in combination with tools and extensions of standard Gaussian Processes such as principled hyperparameter estimation, sparsification, and quantile regression with input-dependent noise rates. No existing approach enjoys all of these desirable properties. Experiments on benchmark datasets show that our method is competitive with state-of-the-art approaches. © 2009 IEEE.

200 v superjunction N-type lateral insulated-gate bipolar transistor with improved latch-up characteristics

This paper evaluates the technique used to improve the latching characteristics of the 200 V n-type superjunction (SJ) lateral insulated-gate bipolar transistor (LIGBT) on a partial silicon-on-insulator. SJ IGBT devices are more prone to latch-up than standard IGBTs due to the presence of a strong pnp transistor with the p layer serving as an effective collector of holes. The initial SJ LIGBT design latches at about 23 V with a gate voltage of 5 V with a forward voltage drop (VON) of 2 V at 300 Acm2. The latch-up current density is 1100 Acm2. The latest SJ LIGBT design shows an increase in latch-up voltage close to 100 V without a significant penalty in VON. The latest design shows a latch-up current density of 1195 A cm2. The enhanced robustness against static latch-up leads to a better forward bias safe operating area. © 1963-2012 IEEE.

Characterization of vertical Mo/diamond Schottky barrier diode from non-ideal I-V and C-V measurements based on MIS model

In this study, we investigated non-ideal characteristics of a diamond Schottky barrier diode with Molybdenum (Mo) Schottky metal fabricated by Microwave Plasma Chemical Vapour Deposition (MPCVD) technique. Extraction from forward bias I-V and reverse bias C- 2-V measurements yields ideality factor of 1.3, Schottky barrier height of 1.872 eV, and on-resistance of 32.63 mö·cm2. The deviation of extracted Schottky barrier height from an ideal value of 2.24 eV (considering Mo workfunction of 4.53 eV) indicates Fermi level pinning at the interface. We attributed such non-ideal behavior to the existence of thin interfacial layer and interface states between metal and diamond which forms Metal-Interfacial layer-Semiconductor (MIS) structure. Oxygen surface treatment during fabrication process might have induced them. From forward bias C-V characteristics, the minimum thickness of the interfacial layer is approximately 0.248 nm. Energy distribution profile of the interface state density is then evaluated from the forward bias I-V characteristics based on the MIS model. The interface state density is found to be uniformly distributed with values around 1013 eV - 1·cm- 2. © 2013 Elsevier B.V.

The effects of non-unity lewis numbers on turbulent premixed flame interactions in a twin V-flame configuration

The influence of Lewis number on turbulent premixed flame interactions is investigated using automatic feature extraction (AFE) applied to high-resolution flame simulation data. Premixed turbulent twin V-flames under identical turbulence conditions are simulated at global Lewis numbers of 0.4, 0.8, 1.0, and 1.2. Information on the position, frequency, and magnitude of the interactions is compared, and the sensitivity of the results to sample interval is discussed. It is found that both the frequency and magnitude of normal type interactions increases with decreasing Lewis number. Counternormal type interactions become more likely as the Lewis number increases. The variation in both the frequency and the magnitude of the interactions is found to be caused by large-scale changes in flame wrinkling resulting from differences in the thermo-diffusive stability of the flames. During flame interactions, thermo-diffusive effects are found to be insignificant due to the separation of time scales. © 2013 Copyright Taylor and Francis Group, LLC.

III-V semiconductor nanowires for optoelectronic device applications

Semiconductor nanowires have recently emerged as a new class of materials with significant potential to reveal new fundamental physics and to propel new applications in quantum electronic and optoelectronic devices. Semiconductor nanowires show exceptional promise as nanostructured materials for exploring physics in reduced dimensions and in complex geometries, as well as in one-dimensional nanowire devices. They are compatible with existing semiconductor technologies and can be tailored into unique axial and radial heterostructures. In this contribution we review the recent efforts of our international collaboration which have resulted in significant advances in the growth of exceptionally high quality IIIV nanowires and nanowire heterostructures, and major developments in understanding the electronic energy landscapes of these nanowires and the dynamics of carriers in these nanowires using photoluminescence, time-resolved photoluminescence and terahertz conductivity spectroscopy. © 2011 Elsevier Ltd. All rights reserved.

Phase perfection in zinc Blende and Wurtzite III-V nanowires using basic growth parameters.

Controlling the crystallographic phase purity of III-V nanowires is notoriously difficult, yet this is essential for future nanowire devices. Reported methods for controlling nanowire phase require dopant addition, or a restricted choice of nanowire diameter, and only rarely yield a pure phase. Here we demonstrate that phase-perfect nanowires, of arbitrary diameter, can be achieved simply by tailoring basic growth parameters: temperature and V/III ratio. Phase purity is achieved without sacrificing important specifications of diameter and dopant levels. Pure zinc blende nanowires, free of twin defects, were achieved using a low growth temperature coupled with a high V/III ratio. Conversely, a high growth temperature coupled with a low V/III ratio produced pure wurtzite nanowires free of stacking faults. We present a comprehensive nucleation model to explain the formation of these markedly different crystal phases under these growth conditions. Critical to achieving phase purity are changes in surface energy of the nanowire side facets, which in turn are controlled by the basic growth parameters of temperature and V/III ratio. This ability to tune crystal structure between twin-free zinc blende and stacking-fault-free wurtzite not only will enhance the performance of nanowire devices but also opens new possibilities for engineering nanowire devices, without restrictions on nanowire diameters or doping.

Unexpected benefits of rapid growth rate for III-V nanowires.

In conventional planar growth of bulk III-V materials, a slow growth rate favors high crystallographic quality, optical quality, and purity of the resulting material. Surprisingly, we observe exactly the opposite effect for Au-assisted GaAs nanowire growth. By employing a rapid growth rate, the resulting nanowires are markedly less tapered, are free of planar crystallographic defects, and have very high purity with minimal intrinsic dopant incorporation. Importantly, carrier lifetimes are not adversely affected. These results reveal intriguing behavior in the growth of nanoscale materials, and represent a significant advance toward the rational growth of nanowires for device applications.

III-V compound semiconductor nanowires for optoelectronic device applications

GaAs and InP based III-V compound semiconductor nanowires were grown epitaxially on GaAs (or Si) (111)B and InP (111)B substrates, respectively, by metalorganic chemical vapor deposition using Au nanoparticles as catalyst. In this paper, we will give an overview of nanowire research activities in our group. In particular, the effects of growth parameters on the crystal structure and optical properties of various nanowires were studied in detail. We have successfully obtained defect-free GaAs nanowires with nearly intrinsic exciton lifetime and vertical straight nanowires on Si (111)B substrates. The crystal structure of InP nanowires, i.e., WZ or ZB, can also be engineered by carefully controlling the V/III ratio and catalyst size. © 2011 World Scientific Publishing Company.

Au-catalyzed InP nanowires: The influence of growth temperature and V/III ratio

Growth of Au-catalyzed InP nanowires (NWs) by metalorganic chemical vapor deposition (MOCVD) has been studied in the temperature range of 400-510 °C and V/III ratio of 44-700. We demonstrate that minimal tapering of InP NWs can be achieved at 400 °C and V/III ratio of 350. Zinc-blende (ZB) or wurtzite (WZ) NWs is obtained depending on the growth conditions. 4K microphotoluminescence (μ-PL) studies show that emission energy is blue-shifted as growth temperature increases. By changing these growth parameters, one can tune the emission wavelength of InP NWs which is attractive for applications in developing novel optoelectronic devices. © 2010 IEEE.

Growth temperature and V/III ratio effects on the morphology and crystal structure of InP nanowires

The effects of growth temperature and V/III ratio on the morphology and crystallographic phases of InP nanowires that are grown by metal organic chemical vapour deposition have been studied. We show that higher growth temperatures or higher V/III ratios promote the formation of wurtzite nanowires while zinc-blende nanowires are favourableat lower growth temperatures and lower V/III ratios. A schematic map of distribution of zinc-blende and wurtzite structures has been developed in the range of growth temperatures (400-510 °C) and V/III ratios (44 to 700) investigated in this study. © 2010 IOP Publishing Ltd.

III-V compound semiconductor nanowires

InP and GaAs based nanowires were grown epitaxially on InP or GaAs (111)B substrates by metalorganic chemical vapor deposition via vapor-liquid-solid (VLS) mechanism. In this report, I will give an overview of nanowire research activities in our group. In particular, the effects of growth parameters for InP and GaAs nanowires on the crystal quality have been studied in detail. We demonstrated the ability to obtain defect-free GaAs nanowires and control the crystal structure of InP nanowires, ie, WZ or ZB, by choosing a combination of growth parameters, such as temperature, V/III ratio and nanowire diameter. © 2009 IEEE NANO Organizers.

III-V compound semiconductor nanowires

GaAs and InP based nanowires were grown epitaxially on GaAs or InP (111)B substrates by metalorganic chemical vapor deposition using Au nanoparticles as catalyst. In this talk, I will give an overview of nanowire research activities in our group. Especially, the effects of growth parameters for GaAs and InP nanowires on the crystal quality have been studied in detail. We demonstrated the ability to obtain defect-free GaAs nanowires and control the crystal structure of InP nanowires, ie, WZ or ZB, by choosing a combination of growth parameters, such as temperature, V/III ratio and nanowire diameter. © 2009 IEEE.