Tubular graphite cones with single-crystal nanotips and their antioxygenic properties.

Tubular graphite cones (TGCs) with a single-crystal nanotip have been achieved by means of microwave plasma-assisted chemical vapor deposition using in-situ-evaporated Fe catalysts. The absence of the disorder-induced D band in Raman spectra revealed the single-crystalline feature of the nanotip. TGCs were found to stem from Fe catalytic carbon spherules on the order of 100 mum diameter, whose critical role in promoting both nucleation and plasma annealing in the formation of highly crystalline TGCs is discussed. The crystalline quality of such TGCs can be further verified by the investigation of their oxidative stability in air. All TGCs can survive up to 600 degrees C without any structural variations, and a few TGCs still survive with an anisotropic etched and stepped nanotip at temperatures up to 800 degrees C, much better than CNTs. Thus, TGCs with single crystalline nanotips are potential candidates for scanning probes in high-temperature oxygen-containing environments.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

Effect of deposition conditions on the chemical bonding in sputtered carbon nitride films

A balanced planar r.f. powered magnetron sputter source has been used to deposit carbon nitride films from a graphite target under various conditions. Sample temperature, bias voltage and nitrogen content in the gas mixture were varied. The effects of oxygen, methane and ammonia on the film growth were also studied. Special attention was paid to the effects of the deposition parameters on the structure of the films, in particular the hybridisation of the carbon and nitrogen bonding. The chemical bonding of the carbon and nitrogen atoms was studied by electron energy loss spectroscopy (EELS). The chemical composition was evaluated by Rutherford back-scattering. The intensity of transitions to π antibonding orbitals, as revealed by EELS, was found to increase with the nitrogen content in the films. Ion bombardment of the films during growth and the addition of oxygen or hydrogen-rich gases further increased the proportion of π bonds of both the carbon and nitrogen atoms. It is suggested that the increase in the transitions to μ antibond orbitals is to be explained by increased sp2 or possibly sp hybridisation of the carbon and nitrogen. Also, the effect of annealing on the bonding of nitrogen rich films after deposition was tested. The changes caused by nitrogen and deposition conditions are consistent with previous reports on the formation of paracyanogen structures.

Application of electron beams in thermal processing of semiconductor materials and devices

Rapid and effective thermal processing methods using electron beams are described in this paper. Heating times ranging from a fraction of a second to several seconds and temperatures up to 1400°C are attainable. Applications such as the annealing of ion implanted material, both without significant dopant diffusion and with highly controlled diffusion of impurities, are described. The technique has been used successfully to activate source/drain regions for fine geometry NMOS transistors. It is shown that electron beams can produce localised heating of semiconductor substrates and a resolution of approximately 1 μm has been achieved. Electron beam heating has been applied to improving the crystalline quality of silicon-on sapphire used in CMOS device fabrication. Silicon layers with defect levels approaching bulk material have been obtained. Finally, the combination of isothermal and selective annealing is shown to have application in recrystallisation of polysilicon films on an insulating layer. The approach provides the opportunity of producing a silicon-on-insulator substrate with improved crystalline quality compared to silicon-on-sapphire at a potentially lower cost. It is suggested that rapid heating methods are expected to provide a real alternative to conventional furnace processing of semiconductor devices in the development of fabrication technology. © 1984 Benn electronics Publications Ltd, Luton.

EFFECT OF GRAIN-BOUNDARY MICROSTRUCTURE ON CAVITY NUCLEATION IN A NICKEL-BASED SUPERALLOY.

A study is presented of grain-boundary cavitation produced in Nimonic 80A by cold-deformation and stress-free annealing. The cavities were found to originate either from transverse cracking of carbide particles, or from decohesion of the particle-grain boundary interfaces. This decohesion could occur either during deformation, or during annealing. The cavities were invariably located at or close to the point of impingement of a matrix slip band on the grain boundary, but not all slip bands at a particular boundary were associated with cavitation. Quantitative evidence is presented showing that the mean number of dislocations associated with each slip band increases with macroscopic strain, but there is considerable variation between slip bands. This accounts for the differential ability of slip bands to result in cavity nucleation.

Performance of CMOS Devices in Silicon-on-Sapphire Films After Solid-Phase Epitaxial Growth With Rapid Electron-Beam Heating

The crystal quality of 0.3-μm-thick as-grown epitaxial silicon-on-sapphire (SOS) was improved using solid-phase epitaxy (SPE) by implantation with silicon to 1015 ions/cm2 at 175 keV and rapid annealing using electron-beam heating, n-channel and p-channel transistormobilities increased by 31 and 19 percent, respectively, and a reduction in ring-oscillator stage delay confirmed that crystal defects near the upper silicon surface had been removed. Leakage in n-channel transistors was not significantly affected by the regrowth process but for p-channel transistors back-channel leakage was considerably greater than for the control devices. This is attributed to aluminum released by damage to the sapphire during silicon implantation. © 1985 IEEE

REGROWTH RATES OF AMORPHOUS LAYERS IN SILICON-ON-SAPPHIRE FILMS.

The rate and direction of regrowth of amorphous layers, created by self-implantation, in silicon-on-sapphire (SOS) have been studied using time resolved reflectivity (TRR) experiments performed simultaneously at two wavelengths. Regrowth of an amorphous layer towards the surface was observed in specimens implanted with 3 multiplied by (times) 10**1**5Si** plus /cm**2 at 50keV and regrowth of a buried amorphous layer, from a surface seed towards the sapphire, was observed in specimens implanted with 1 multiplied by (times) 10**1**5Si** plus /cm**2 at 175keV. Rapid isothermal heating to regrow the layers was performed in an electron beam annealing system. The combination of 514. 5nm and 632. 8nm wavelengths was found to be particularly useful for TRR studies since the high absorption in amorphous silicon, at the shorter wavelength, means that the TRR trace is not complicated by reflection from the silicon-sapphire interface until regrowth is nearly complete.

Mechanism of polarization pinning in vertical cavity surface emitting lasers using focused ion beam etching

Photoluminescence experiments have identified strain as the origin for polarization pinning in vertical cavity surface emitting lasers post-processed by focused ion beam etching. Theoretical models were applied to deduce the strain in devices. Post-annealing was used to optimize polarization pinning.

Three band-gap QW intermixing in InP/InGaAs/InGaAsP system for monolithically integrated optical switch

Quantum well intermixing is a key technique for photonic integration. The intermixing of InP/InGaAs/InGaAsP material involving the deposition of a layer of sputtered SiO2 on the semiconductor surface, followed by thermal annealing has allowed good control of the intermixing process and has been used to fabricate extended cavity lasers. This will be used for optimization of the performance of optical switches consisting of passive components, modulators and amplifiers.

Characterization of defect removal in hydrogenated and deuterated amorphous silicon thin film transistors

Thin film transistors (TFTs) utilizing an hydrogenated amorphous silicon (a-Si:H) channel layer exhibit a shift in the threshold voltage with time under the application of a gate bias voltage due to the creation of metastable defects. These defects are removed by annealing the device with zero gate bias applied. The defect removal process can be characterized by a thermalization energy which is, in turn, dependent upon an attempt-to-escape frequency for defect removal. The threshold voltage of both hydrogenated and deuterated amorphous silicon (a-Si:D) TFTs has been measured as a function of annealing time and temperature. Using a molecular dynamics simulation of hydrogen and deuterium in a silicon network in the H2 * configuration, it is shown that the experimental results are consistent with an attempt-to-escape frequency of (4.4 ± 0.3) × 1013 Hz and (5.7 ± 0.3) × 1013 Hz for a-Si:H and a-Si:D respectively which is attributed to the oscillation of the Si-H and Si-D bonds. Using this approach, it becomes possible to describe defect removal in hydrogenated and deuterated material by the thermalization energies of (1.552 ± 0.003) eV and (1.559 ± 0.003) eV respectively. This correlates with the energy per atom of the Si-H and Si-D bonds. © 2006 Elsevier B.V. All rights reserved.

Vertically aligned carbon nanotubes growth using self-assembled Ni nanoparticles produced by ion implantation

An alternative method for seeding catalyst nanoparticles for carbon nanotubes and nanowires growth is presented. Ni nanoparticles are formed inside a 450 nm SiO2 film on (100) Si wafers through the implantation of Ni ions at fluences of 7.5×1015 and 1.7×1016 ions.cm-2 and post-annealing treatments at 700, 900 and 1100°C. After exposed to the surface by HF dip etching, the Ni nanoparticles are used as catalyst for the growth of vertically aligned carbon nanotubes by direct current plasma enhanced chemical vapor deposition. © 2007 Materials Research Society.

Millisecond processing beyond chip technology: From electronics to photonics

There is a clear and increasing interest in short time annealing processing far below one second, i.e. the lower limit of Rapid Thermal Processing (RTP) called spike annealing. This was driven by the need of suppressing the so-called Transient Enhanced Diffusion in advanced boronimplanted shallow pn-junctions in silicon technology. Meanwhile the interest in flash lamp annealing (FLA) in the millisecond range spread out into other fields related to silicon technology and beyond. This paper reports on recent experiments regarding shallow junction engineering in germanium, annealing of ITO layers on glass and plastic foil to form an conductive layer as well as investigations which we did during the last years in the field of wide band gap semiconductor materials (SiC, ZnO). A more common feature evolving from our work was related to the modeling of wafer stress during millisecond thermal processing with flash lamps. Finally recent achievements in the field of silicon-based light emission basing on Metal-Oxide-Semiconductor Light Emitting Devices will be reported. © 2007 IEEE.

Advanced thermal processing of semiconductor materials in the msec-range

This paper reviews the advances that flash lamp annealing brings to the processing of the most frequently used semiconductor materials, namely silicon and silicon carbide, thus enabling the fabrication of novel microelectronic structures and materials. The paper describes how such developments can translate into important practical applications leading to a wide range of technological benefits. Opportunities in ultra-shallow junction formation, heteroepitaxial growth of thin films of cubic silicon carbide on silicon, and crystallization of amorphous silicon films, along with the technical reasons for using flash lamp annealing are discussed in the context of state-of-the-art materials processing. © 2005 IEEE.

Thin film shape memory alloys and microactuators

For Micro-electro-mechanical System (MEMS) applications, TiNi-based thin film Shape Memory Alloys (SMAs) possess many desirable properties, such as high power density, large transformation stress and strain upon heating and cooling, superelasticity and biocompatibility. In this paper, recent development in TiNi-based thin film SMA and microactuator applications is discussed. The topics related to film deposition and characterisation is mainly focused on crystal nucleation and growth during annealing, film thickness effect, film texture, stress induced surface relief, wrinkling and trenches as well as Temperature Memory Effect (TME). The microactuator applications are mainly focused on microvalve and microcage for biological applications, micromirror for optical applications and data storage using nanoindentation method. Copyright © 2009, Inderscience Publishers.

Electric conduction improvement of well-structured multi-walled carbon nanotubes

We characterized the electrical conductance of well-structured multi-walled carbon nanotubes (MWCNTs) which had post-treated by a rapid vacuum arc thermal annealing process and structure defects in these nanotubes are removed. We found that the after rapid vacuum arc annealing, the conductivity of well-structured MWCNTs can be improved by an order of magnitude. We also investigated the conductivity of MWCNTs bundle by the variation of temperatures. These results show that the conductance of annealed defect-free MWCNTs is sensitive to temperature imply the phonon scatting dominated the electron conductions. Compare to the well-structured MWCNTs, the defect scattering dominated the electron conduction in the as-grown control sample which has large amount of structure defects. A detail measurement of electron conduction from an individual well-structured MWCNT shows that the conductivity increases with temperatures which imply such MWCNTs exhibited semiconductor properties. We also produced back-gated field-effect transistors using these MWCNTs. It shows that the well-structured MWCNT can act as p-type semiconductor. © 2010 IEEE.