High-resolution strain sensing on steel by Silicon-On-Insulator flexural resonators fabricated with chip-level vacuum packaging

This paper reports on the fabrication and characterization of high-resolution strain sensors for steel based on Silicon On Insulator flexural resonators manufactured with chip-level LPCVD vacuum packaging. The sensors present high sensitivity (120 Hz/μ), very high resolution (4 n), low drift, and near-perfect reversibility in bending tests performed in both tensile and compressive strain regimes. © 2013 IEEE.

First human hNT neurons patterned on parylene-C/silicon dioxide substrates: Combining an accessible cell line and robust patterning technology for the study of the pathological adult human brain

In this communication, we describe a new method which has enabled the first patterning of human neurons (derived from the human teratocarcinoma cell line (hNT)) on parylene-C/silicon dioxide substrates. We reveal the details of the nanofabrication processes, cell differentiation and culturing protocols necessary to successfully pattern hNT neurons which are each key aspects of this new method. The benefits in patterning human neurons on silicon chip using an accessible cell line and robust patterning technology are of widespread value. Thus, using a combined technology such as this will facilitate the detailed study of the pathological human brain at both the single cell and network level. © 2010 Elsevier B.V.

Patterning and detailed study of human hNT astrocytes on parylene-C/silicon dioxide substrates to the single cell level.

It is estimated that the adult human brain contains 100 billion neurons with 5-10 times as many astrocytes. Although it has been generally considered that the astrocyte is a simple supportive cell to the neuron, recent research has revealed new functionality of the astrocyte in the form of information transfer to neurons of the brain. In our previous work we developed a protocol to pattern the hNT neuron (derived from the human teratocarcinoma cell line (hNT)) on parylene-C/SiO(2) substrates. In this work, we report how we have managed to pattern hNT astrocytes, on parylene-C/SiO(2) substrates to single cell resolution. This article disseminates the nanofabrication and cell culturing steps necessary for the patterning of such cells. In addition, it reports the necessary strip lengths and strip width dimensions of parylene-C that encourage high degrees of cellular coverage and single cell isolation for this cell type. The significance in patterning the hNT astrocyte on silicon chip is that it will help enable single cell and network studies into the undiscovered functionality of this interesting cell, thus, contributing to closer pathological studies of the human brain.

Selective epitaxial growth in silicon on insulator: Planarity and mass flow

Seeded zone-melt recrystallization using a dual electron beam system has been performed on silicon-on-insulator material, which was prepared with single-crystal silicon filling of the seed windows by selective epitaxial growth. The crystal quality has been assessed by a variety of microscopic techniques, and it is shown that single-crystal films 0.5-1.0 μm thick over 1.0 μm of isolating oxide may be prepared by this method. These films have considerably less lateral variation in thickness than standard material, in which the windows are not so filled. The filling method is suitable for both single- and multiple-layer silicon-on-insulator, and gives the advantages of excellent layer uniformity after recrystallization and improved planarity of the whole chip structure. Experiments using various amounts of seed window filling have shown that the lateral variations of silicon film thickness seen in unplanarized material are due to stress relief in the cap oxide when the silicon film is molten, rather than the effect previously postulated in which they were assumed to be due to the contraction of silicon on melting.

Millisecond processing beyond chip technology: From electronics to photonics

There is a clear and increasing interest in short time annealing processing far below one second, i.e. the lower limit of Rapid Thermal Processing (RTP) called spike annealing. This was driven by the need of suppressing the so-called Transient Enhanced Diffusion in advanced boronimplanted shallow pn-junctions in silicon technology. Meanwhile the interest in flash lamp annealing (FLA) in the millisecond range spread out into other fields related to silicon technology and beyond. This paper reports on recent experiments regarding shallow junction engineering in germanium, annealing of ITO layers on glass and plastic foil to form an conductive layer as well as investigations which we did during the last years in the field of wide band gap semiconductor materials (SiC, ZnO). A more common feature evolving from our work was related to the modeling of wafer stress during millisecond thermal processing with flash lamps. Finally recent achievements in the field of silicon-based light emission basing on Metal-Oxide-Semiconductor Light Emitting Devices will be reported. © 2007 IEEE.

A packaging technique for silicon MEMS strain sensors on steel

A packaging technique suited to applying MEMS strain sensors realized on a silicon chip to a steel flat surface is described. The method is based on adhesive bonding of the silicon chip rear surface on steel using two types of glue normally used for standard piezoresistive strain sensors (Mbond200/ 600), using direct wire bonding of the chip to a Printed Circuit Board, also fixed on steel. In order to protect the sensor from the external environment, and to improve the MEMS performance, the silicon chip is encapsulated with a metal cap hermetically sealed-off under vacuum condition with a vacuum adhesive in which the bonding wires are also protected from possible damage. In order to evaluate the mechanical coupling of the silicon chip with the bar and thestress transfer extent to the silicon surface, commercial strain sensors have been applied on the chip glued on a steel bar in alaboratory setup able to generate strain by inflection, yielding a stress transfer around 70% from steel to silicon. © 2008 IEEE.

Soft turn-on of NPT IGBT under Active Voltage Control

In this paper the soft turn-on of NPT IGBT under Active Voltage Control (AVC) is presented. The AVC technique is able to control the IGBT switching trajectory according to a pre-defined reference signal generated by a FPGA chip. By applying a special designed reference signal at turn-on, the IGBT turn-on current overshoot and diode recovery can be optimized. Experiments of soft turn-on with different reference signal are presented in this paper. This technique can be used to reduce the switching stress on the device and on other components of the circuit. © 2011 IEEE.

Guided growth of neurons and glia using microfabricated patterns of parylene-C on a SiO2 background.

This paper describes a simple technique for the patterning of glia and neurons. The integration of neuronal patterning to Multi-Electrode Arrays (MEAs), planar patch clamp and silicon based 'lab on a chip' technologies necessitates the development of a microfabrication-compatible method, which will be reliable and easy to implement. In this study a highly consistent, straightforward and cost effective cell patterning scheme has been developed. It is based on two common ingredients: the polymer parylene-C and horse serum. Parylene-C is deposited and photo-lithographically patterned on silicon oxide (SiO(2)) surfaces. Subsequently, the patterns are activated via immersion in horse serum. Compared to non-activated controls, cells on the treated samples exhibited a significantly higher conformity to underlying parylene stripes. The immersion time of the patterns was reduced from 24 to 3h without compromising the technique. X-ray photoelectron spectroscopy (XPS) analysis of parylene and SiO(2) surfaces before and after immersion in horse serum and gel based eluant analysis suggests that the quantity and conformation of proteins on the parylene and SiO(2) substrates might be responsible for inducing glial and neuronal patterning.

Low on-resistance SOI dual-trench-gate MOSFET

A low specific on-resistance (R-{{\rm on}, {\rm sp}}) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation. The SOI MOSFET features double trenches and dual gates (DTDG SOI): an oxide trench in the drift region, a buried gate inset in the oxide trench, and another trench gate (TG) extended to a buried oxide layer. First, the dual gates form dual conduction channels, and the extended gate widens the vertical conduction area; both of which sharply reduce R-{{\rm on}, {\rm sp}}. Second, the oxide trench folds the drift region in the vertical direction, resulting in a reduced device pitch and R-{{\rm on}, {\rm sp}}. Third, the oxide trench causes multidirectional depletion. This not only enhances the reduced surface field effect and thus reshapes the electric field distribution but also increases the drift doping concentration, leading to a reduced R-{{\rm on}, {\rm sp}} and an improved breakdown voltage (BV). Compared with a conventional SOI lateral Double-diffused metal oxide semiconductor (LDMOS), the DTDG MOSFET increases BV from 39 to 92 V at the same cell pitch or decreases R-{{\rm on}, { \rm sp}} by 77% at the same BV by simulation. Finally, the TG extended synchronously acts as an isolation trench between the high/low-voltage regions in a high-voltage integrated circuit, saving the chip area and simplifying the isolation process. © 2006 IEEE.

Cost-effective 10 Gb/s polymer-based chip-to-chip optical interconnect

Board-level optical links are an attractive alternative to their electrical counterparts as they provide higher bandwidth and lower power consumption at high data rates. However, on-board optical technology has to be cost-effective to be commercially deployed. This study presents a chip-to-chip optical interconnect formed on an optoelectronic printed circuit board that uses a simple optical coupling scheme, cost-effective materials and is compatible with well-established manufacturing processes common to the electronics industry. Details of the link architecture, modelling studies of the link's frequency response, characterisation of optical coupling efficiencies and dynamic performance studies of this proof-of-concept chip-to-chip optical interconnect are reported. The fully assembled link exhibits a -3 dBe bandwidth of 9 GHz and -3 dBo tolerances to transverse component misalignments of ±25 and ±37 μm at the input and output waveguide interfaces, respectively. The link has a total insertion loss of 6 dBo and achieves error-free transmission at a 10 Gb/s data rate with a power margin of 11.6 dBo for a bit-error-rate of 10 -12. The proposed architecture demonstrates an integration approach for high-speed board-level chip-to-chip optical links that emphasises component simplicity and manufacturability crucial to the migration of such technology into real-world commercial systems. © 2012 The Institution of Engineering and Technology.