Advantages of top-gate, high-k dielectric carbon nanotube field-effect transistors

The subthreshold slope, transconductance, threshold voltage, and hysteresis of a carbon nanotube field-effect transistor (CNT FET) were examined as its configuration was changed from bottom-gate exposed channel, bottom-gate covered channel to top-gate FET. An individual single wall CNT was grown by chemical vapor deposition and its gate configuration was changed while determining its transistor characteristics to ensure that the measurements were not a function of different chirality or diameter CNTs. The bottom-gate exposed CNT FET utilized 900 nm SiO2 as the gate insulator. This CNT FET was then covered with TiO2 to form the bottom-gate covered channel CNT FET. Finally, the top-gate CNT FET was fabricated and the device utilized TiO 2 (K ∼ 80, equivalent oxide thickness=0.25 nm) as the gate insulator. Of the three configurations investigated, the top-gate device exhibited best subthreshold slope (67-70 mV/dec), highest transconductance (1.3 μS), and negligible hysteresis in terms of threshold voltage shift. © 2006 American Institute of Physics.

Modeling of MOS-side carrier injection in trench-gate IGBTs

A compact trench-gate IGBT model that captures MOS-side carrier injection is developed. The model retains the simplicity of a one-dimensional solution to the ambipolar diffusion equation, but at the same time captures MOS-side carrier injection and its effects on steady-state carrier distribution in the drift region and on switching waveforms. © 2007 IEEE.

Effect of gate dielectric scaling in nanometer scale vertical thin film transistors

A short channel vertical thin film transistor (VTFT) with 30 nm SiN x gate dielectric is reported for low voltage, high-resolution active matrix applications. The device demonstrates an ON/OFF current ratio as high as 10 9, leakage current in the fA range, and a sub-threshold slope steeper than 0.23 V/dec exhibiting a marked improvement with scaling of the gate dielectric thickness. © 2011 American Institute of Physics.

Polymer gate dielectrics with self-assembled monolayers for high-mobility organic thin-film transistors based on copper phthalocyanine

Organic thin-film transistors based on polycrystalline copper phthalocyanine (CuPc) were fabricated by using poly(vinyl alcohol) as gate dielectric. After treatment of the gate dielectric using an octadecyltrichlorosilane self-assembled monolayer, a mobility of up to 0.11 cm2/V∈s was achieved, which is comparable to that of single-crystal CuPc devices (0.1-1 cm2/V∈s). The surface morphology was analyzed and the possible reasons for the enhanced mobility are discussed. © 2009 Springer-Verlag.