Trench insulated gate bipolar transistor - a high power switching device

This paper presents a comprehensive theoretical study of the Trench Insulated Gate Bipolar Transistors (TIGBT). Specific physical and geometrical effects, such as the accumulation layer injection, increased channel density, increased channel charge and transversal electric field modulation are discussed. The potential advantages of the Trench IGBT over its conventional planar variant are highlighted. It is concluded that the Trench IGBT is one of the most promising structures in the area of high voltage MOS-controllable switching devices.

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An ingenious new CMOS-compatible process which promises to significantly improve the performance of power devices is discussed. A novel power device concept based on the use of high voltage regions suspended on thin semiconductor/dielectric membranes is reported. The membrane power devices are manufactured in a fully-CMOS compatible silicon-on-insulator (SOI) process followed by a bulk etching step and subsequent back-passivation. The concept is applicable to a class of high voltage devices such as LDMOSFETs, diodes, LIGBTs and superjunctions.

MOS and bipolar gated thyristor: A thyristor with IGBT switching characteristics

The IGBT has become the device of choice in many high-voltage-power electronic applications, by virtue of combining the ease of MOS gate control with an acceptable forward voltage drop. However, designers have retained an interest in MOS gated thyristor structures which have a turn-off capability. These offer low on-state losses as a result of their latching behaviour. Recently, there have been various proposals for dual-gate devices that have a thyristor on-state with IGBT-like switching. Many of these dual gated structures rely on advanced MOS technology, with inherent manufacturing difficulties. The MOS and bipolar gated thyristor offers all the advantages of dual gated performance, while employing standard IGBT processing techniques. The paper describes the MBGT in detail, and presents experimental and simulation results for devices based on realistic commercial processes. It is shown that the MBGT represents a viable power semiconductor device technology, suitable for a diverse range of applications. © IEE, 1998.

Physical modelling of large area 4H-SiC PiN diodes

The recent developments in SiC PiN diode research mean that physics-based models that allow accurate, rapid prediction of switching and conduction performance and resulting converter losses will soon be required. This is especially the case given the potential for very high voltage converters to be used for enabling distributed and renewable power generation. In this work an electro-thermal compact model of a 4.5 kV silicon carbide PiN diode has been developed for converter loss modelling in Simulink. Good matching of reverse recovery has been achieved between 25 and 200 °C. The I-V characteristics of the P+ anode contact have been shown to be significant in obtaining good matching for the forward characteristics of the diode, requiring further modelling work in this area. © 2009 IEEE.

Investigation into IGBT dV/dt during turn-off and its temperature dependence

In many power converter applications, particularly those with high variable loads, such as traction and wind power, condition monitoring of the power semiconductor devices in the converter is considered desirable. Monitoring the device junction temperature in such converters is an essential part of this process. In this paper, a method for measuring the insulated gate bipolar transistor (IGBT) junction temperature using the collector voltage dV/dt at turn-OFF is outlined. A theoretical closed-form expression for the dV/dt at turn-OFF is derived, closely agreeing with experimental measurements. The role of dV/dt in dynamic avalanche in high-voltage IGBTs is also discussed. Finally, the implications of the temperature dependence of the dV/dt are discussed, including implementation of such a temperature measurement technique. © 2006 IEEE.

Spinning off a semiconductor company from University premises -The story of Camsemi

The spinning off of Cambridge Semiconductor Ltd (Camsemi) from the High Voltage Microelectronics Lab at Cambridge University is discussed. The technology originated from Cambridge University and was subsequently developed and commercialized as PowerBrane by Camsemi. The paper also discusses the business model and the enabling financial factors that led to the formation of Camsemi as a fables IC company, including access to seed funding from University and the subsequent investments of venture capital in several rounds. © 2011 IEEE.

Design and optimization of a 250nm SOI LDMOSFET

This work is aimed at optimising the static performance of a high voltage SOI LDMOSFET. Starting with a conventional LDMOSFET, 2D and 3D numerical simulation models, able to accurately match datasheet values, have been developed. Moving from the original device, several design techniques have been investigated with the target of improving the breakdown voltage and the ON-state resistance. The considered design techniques are based on the modification of the doping profile of the drift region and the Superjunction design technique. The paper shows that a single step doping within the drift region is the best design choice for the considered device and is found to give a 24% improvement in the breakdown voltage and a 17% reduction of the ON-state resistance. © 2011 IEEE.

Steady-state analytical model for the trench insulated gate bipolar transistor

A steady-state, physically-based analytical model for the Trench Insulated Gate Bipolar Transistor which accounts for a combined PIN diode - PNP transistor carrier dynamics is proposed. Previous models (i.e. PIN model and PNP transistor model) cannot account properly for the carrier dynamics in Trench IGBT since neither the PNP transistor nor the PIN diode effect can be neglected. An optimized Trench IGBT with a large ratio between the accumulation layer and the cell size leads to substantially improved on-state characteristics, which makes the Trench IGBT potentially the most attractive device in the area of high voltage fast switching devices.

Low on-resistance SOI dual-trench-gate MOSFET

A low specific on-resistance (R-{{\rm on}, {\rm sp}}) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation. The SOI MOSFET features double trenches and dual gates (DTDG SOI): an oxide trench in the drift region, a buried gate inset in the oxide trench, and another trench gate (TG) extended to a buried oxide layer. First, the dual gates form dual conduction channels, and the extended gate widens the vertical conduction area; both of which sharply reduce R-{{\rm on}, {\rm sp}}. Second, the oxide trench folds the drift region in the vertical direction, resulting in a reduced device pitch and R-{{\rm on}, {\rm sp}}. Third, the oxide trench causes multidirectional depletion. This not only enhances the reduced surface field effect and thus reshapes the electric field distribution but also increases the drift doping concentration, leading to a reduced R-{{\rm on}, {\rm sp}} and an improved breakdown voltage (BV). Compared with a conventional SOI lateral Double-diffused metal oxide semiconductor (LDMOS), the DTDG MOSFET increases BV from 39 to 92 V at the same cell pitch or decreases R-{{\rm on}, { \rm sp}} by 77% at the same BV by simulation. Finally, the TG extended synchronously acts as an isolation trench between the high/low-voltage regions in a high-voltage integrated circuit, saving the chip area and simplifying the isolation process. © 2006 IEEE.

Superconducting fault current limiter design using parallel-connected YBCO thin films

Superconducting Fault Current Limiters (SFCLs) are able to reduce fault currents to an acceptable value, reducing potential mechanical and thermal damage to power system apparatus and allowing more flexibility in power system design and operation. The device can also help avoid replacing circuit breakers whose capacity has been exceeded. Due to limitations in current YBCO thin film manufacturing processes, it is not easy to obtain one large thin film that satisfies the specifications for high voltage and large current applications. The combination of standardized thin films has merit to reduce costs and maintain device quality, and it is necessary to connect these thin films in different series and parallel configurations in order to meet these specifications. In this paper, the design of a resistive type SFCL using parallel-connected YBCO thin films is discussed, including the role of a parallel resistor and the influence of individual thin film characteristics, based on both theory and experimental results. © 2009 IEEE.

200-V lateral superjunction LIGBT on partial SOI

This letter presents a novel lateral superjunction lateral insulated-gate bipolar transistor (LIGBT) in partial silicon-on-insulator (SOI) technology in 0.18-μm partial-SOI (PSOI) high-voltage (HV) process. For an n-type superjunction LIGBT, the p-layer in the superjunction drift region not only helps in achieving uniform electric field distribution but also contributes to the on-state current. The superjunction LIGBT successfully achieves a breakdown voltage (BV) of 210 V with an R dson of 765 mΩ ̇ mm 2. It exhibits half the value of specific on-state resistance R dson and three times higher saturation current (I dsat) for the same BV, compared to a comparable lateral superjunction laterally diffused metal-oxide-semiconductor fabricated in the same technology. It also performs well in higher temperature dc operation with 38.8% increase in R dson at 175°C, compared to the room temperature without any degradation in latch-up performance. To realize this device, it only requires one additional mask layer into X-FAB 0.18-μm PSOI HV process. © 2012 IEEE.

Design and optimization of planar mesa termination for diamond Schottky barrier diodes

In this paper, we present planar mesa termination structure with high k dielectric Al2O3 for high-voltage diamond Schottky barrier diode. Analysis, design, and optimization are carried out by simulations using finite element technology computer-aided design (TCAD) Sentaurus Device software. The performances of planar mesa termination structure are compared to those of conventional field plate termination structure. It is found that optimum geometry of planar mesa terminated diode requires shorter metal plate extension (1/3 of the field plate terminated diode). Consequently, planar mesa terminated diode can be designed with bigger Schottky contact to increase its current carrying capability. Breakdown performance of field plate termination structure is limited at 1480 V due to peak electric field at the corner of Schottky contact (no oxide breakdown occurs). In contrast, peak electric field in planar mesa termination structure only occurs in the field oxide such that its breakdown performance is highly dependent on the oxide material. Due to Al2O3 breakdown, planar mesa termination structure suffers premature breakdown at 1440 V. Considering no oxide breakdown occurs, planar mesa termination structure can realize higher breakdown voltage of 1751 V. Therefore, to fully realize the potential of planar mesa terminated diode, it is important to choose suitable high k dielectric material with sufficient breakdown electric field for the field oxide. © 2013 Elsevier B.V.

Local lifetime engineering in 600V pin diode using mix-mode simulation

This paper reports a detailed analysis of the effect of local lifetime killing (LLK) within the drift region on the reverse recovery (RR) characteristics and on-state performance of 600V Silicon PiN diodes. The paper also discusses the influence of the measurement circuit on the reverse recovery of the high voltage diodes and it proposes a simple and effective mix-mode simulation tool for an accurate assessment of the diode performance in reverse recovery mode. © 2013 IEEE.

On the variation of the 2DEG charge density with the density of the surface donor traps in AiGaN/GaN transistors

Gallium nitride (GaN) has a bright future in high voltage device owing to its remarkable physical properties and the possibility of growing heterostructures on silicon substrates. GaN High Electron Mobility Transistors (HEMTs) are expected to make a strong impact in off line applications and LED drives. However, unlike in silicon-based power devices, the on-state resistance of HEMT devices is hugely influenced by donor and acceptor traps at interfaces and in the bulk. This study focuses on the influence of donor traps located at the top interface between the semiconductor layer and the silicon nitride on the 2DEG density. It is shown through TCAD simulations and analytical study that the 2DEG charge density has an 'S' shape variation with two distinctive 'flat' regions, wherein it is not affected by the donor concentration, and one linear region. wherein the channel density increases proportionally with the donor concentration. We also show that the upper threshold value of the donor concentration within this 'S' shape increases significantly with the AIGaN thickness and the Al mole fraction and is highly affected by the presence of a thin GaN cap layer. © 2013 IEEE.