Theoretical and numerical investigation of SiC JFET and MOSFET at 6.5 kV

This paper presents a preliminary theoretical and numerical investigation of 4H-SiC JFET and MOSFET at 6.5 kV. To improve the on-state/breakdown performance of the JFET, buried layers in conjunction with a highly doped buffer layer have been used. Trench technology has been employed for the MOSFET. The devices were simulated and optimized using MEDICI[I] simulator. From the comparison between the two devices, it turns out that the JFET offers a better on-state/breakdown trade-off, while the trench MOSFET has the advantage of MOS-control.

10-Gbits/s all-optical 3R regeneration and format conversion using a gain-switched DFB laser

A strain-compensated multiple quantum well device is used as a DFB laser, this has been optimized for low jitter gain switched operation at 10 GHz. The signal is transmitted down 80 km of standard fiber then amplified, filtered and polarization controlled before being injected into a DFB laser. The purpose of this regeneration process is to gain switch the DFB with the extracted clock signal in order to retime the converted signal. This process also simultaneously converts the input NRZ format to an output RZ data to format and results in a signal whose optical power and extinction ratio are considerably improved by the regeneration process.

10-Gbit/s transmission over 300-m standard multimode fiber using multilevel coding and 2-channel WDM

A combination of multilevel coding schemes and simple two-channel wavelength division multiplexing (WDM) at 1300 and 1550 nm was used to transmit an aggregate of 10 Gbit/s over 300 m of multimode fiber that is typical of that employed in current Local Area Networks (LANs). It was shown that this technique could be a simple solution for achieving 10 Gigabit ethernet links over installed multimode fiber building backbones.

Performance of 10 Gbit/s VCSELs operating at 85°C

Oxide-confined VCSELs that are able to operate at modulation speeds of 10 Gbit/s at operating temperatures up to 85°C are demonstrated. This level of performance makes these VCSELs attractive sources for commercial applications in the computer interconnect industry.

Cost-effective 10 Gb/s polymer-based chip-to-chip optical interconnect

Board-level optical links are an attractive alternative to their electrical counterparts as they provide higher bandwidth and lower power consumption at high data rates. However, on-board optical technology has to be cost-effective to be commercially deployed. This study presents a chip-to-chip optical interconnect formed on an optoelectronic printed circuit board that uses a simple optical coupling scheme, cost-effective materials and is compatible with well-established manufacturing processes common to the electronics industry. Details of the link architecture, modelling studies of the link's frequency response, characterisation of optical coupling efficiencies and dynamic performance studies of this proof-of-concept chip-to-chip optical interconnect are reported. The fully assembled link exhibits a -3 dBe bandwidth of 9 GHz and -3 dBo tolerances to transverse component misalignments of ±25 and ±37 μm at the input and output waveguide interfaces, respectively. The link has a total insertion loss of 6 dBo and achieves error-free transmission at a 10 Gb/s data rate with a power margin of 11.6 dBo for a bit-error-rate of 10 -12. The proposed architecture demonstrates an integration approach for high-speed board-level chip-to-chip optical links that emphasises component simplicity and manufacturability crucial to the migration of such technology into real-world commercial systems. © 2012 The Institution of Engineering and Technology.

Tests for conceptual design of 6.6 kV class superconducting fault current limiter with YBCO thin film elements

A superconducting fault current limiter (SFCL) for 6.6 kV and 400 A installed in a cubicle for a distribution network substation was conceptually designed. The SFCL consists of parallel- and series-connected superconducting YBCO elements and a limiting resistor. Before designing the SFCL, some tests were carried out. The width and length of each element used in the tests are 30 mm and 210 mm, respectively. The element consists of YBCO thin film of about 200 nm in thickness on cerium dioxide (CeO2) as a cap-layer on a sapphire substrate by metal-organic deposition with a protective metal coat. In the tests, characteristics of each element, such as over-current, withstand-voltage, and so on, were obtained. From these characteristics, series and parallel connections of the elements, called units, were considered. The characteristics of the units were obtained by tests. From the test results, a single phase prototype SFCL was manufactured and tested. Thus, an SFCL rated at 6.6 kV and 400 A can be designed. © 2009 IEEE.

Intelligent products in the supply chain - 10 years on

Ten years ago the intelligent product model was introduced as a means of motivating a supply chain in which product or orders were central as opposed to the organizations that stored or delivered them. This notion of a physical product influencing its own movement through the supply chain was enabled by the evolution of low cost RFID systems which promised low cost connection between physical goods and networked information environments. In 2002 the notion of product intelligence was regarded as a useful but rather esoteric construct. However, in the intervening ten years there have been a number of technological advances coupled with an increasingly challenged business environment which make the prospects for intelligent product deployment seem more likely. This paper reviews a number of these developments and assesses their impact on the intelligent product approach. © 2012 IFAC.