Influence of lattice temperature on SOI MOSFET's output characteristics

An explanation for the observed variations in the output behaviour of SOI transistors with different buried oxide thicknesses is presented. At low drain bias, the temperature effects are relatively insignificant while at high drain bias, the temperature effects dominate the nonlinear behaviour of the output characteristics.

Theoretical and numerical investigation of SiC JFET and MOSFET at 6.5 kV

This paper presents a preliminary theoretical and numerical investigation of 4H-SiC JFET and MOSFET at 6.5 kV. To improve the on-state/breakdown performance of the JFET, buried layers in conjunction with a highly doped buffer layer have been used. Trench technology has been employed for the MOSFET. The devices were simulated and optimized using MEDICI[I] simulator. From the comparison between the two devices, it turns out that the JFET offers a better on-state/breakdown trade-off, while the trench MOSFET has the advantage of MOS-control.

Air stable complementary polymer circuits fabricated in ambient condition by inkjet printing

Air stable complementary polymer inverters were demonstrated by inkjet printing of both top-gate electrodes and the semiconductors in ambient conditions. The p-type and n-type polymer semiconductors were also thermally annealed in ambient conditions after printing. The good performance of circuits in ambient condition shows that the transistors are not only air-stable in term of ambient humidity and oxygen, but also inert to ion migration through dielectrics from the printed gate. The result obtained here has further confirmed the feasibility of fabrication of low-cost polymer complementary circuits in a practical environment. © 2011 Elsevier B.V. All rights reserved.

Comparative switching behaviour of silicon transistors and practical silicon carbide transistors

The motivation for our work is to identify a space for silicon carbide (SiC) devices in the silicon (Si) world. This paper presents a detailed experimental investigation of the switching behaviour of silicon and silicon carbide transistors (a JFET and a cascode device comprising a Si-MOSFET and a SiC-JFET). The experimental method is based on a clamped inductive load chopper circuit that puts considerable stress on the device and increases the transient power dissipation. A precise comparison of switching behaviour of Si and SiC devices on similar terms is the novelty of our work. The cascode is found to be an attractive fast switching device, capable of operating in two different configurations whose switching equivalent circuits are proposed here. The effect of limited dv/dt of the Si-MOSFET on the switching of the SiC-JFET in a cascode is also critically analysed.

Low on-resistance SOI dual-trench-gate MOSFET

A low specific on-resistance (R-{{\rm on}, {\rm sp}}) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation. The SOI MOSFET features double trenches and dual gates (DTDG SOI): an oxide trench in the drift region, a buried gate inset in the oxide trench, and another trench gate (TG) extended to a buried oxide layer. First, the dual gates form dual conduction channels, and the extended gate widens the vertical conduction area; both of which sharply reduce R-{{\rm on}, {\rm sp}}. Second, the oxide trench folds the drift region in the vertical direction, resulting in a reduced device pitch and R-{{\rm on}, {\rm sp}}. Third, the oxide trench causes multidirectional depletion. This not only enhances the reduced surface field effect and thus reshapes the electric field distribution but also increases the drift doping concentration, leading to a reduced R-{{\rm on}, {\rm sp}} and an improved breakdown voltage (BV). Compared with a conventional SOI lateral Double-diffused metal oxide semiconductor (LDMOS), the DTDG MOSFET increases BV from 39 to 92 V at the same cell pitch or decreases R-{{\rm on}, { \rm sp}} by 77% at the same BV by simulation. Finally, the TG extended synchronously acts as an isolation trench between the high/low-voltage regions in a high-voltage integrated circuit, saving the chip area and simplifying the isolation process. © 2006 IEEE.