p-MOS controlled lateral thyristor: A MOS controllable thyristor suitable for integration

A novel CMOS compatible lateral thyristor is proposed in this paper. Its thyristor conduction is fully controlled by a p-MOS gate. Loss of MOS control due to parasitic latch-up has been eliminated and triggering of the main thyristor at lower forward current achieved. The device operation has been verified by 2-D numerical simulations and experimental fabrication.

Nanoelectromechanical DRAM for ultra-large-scale integration (ULSI)

A Nanoelectromechanical (NEM) device developed for dynamic random access memory (DRAM) is reported. A vertical nanotube structure is employed to form the electromechanical switch and capacitor structure. The mechanical movement of the nanotube defines 'On' and 'OFF' states and the electrical signals which result lead to charge storage in a vertical capacitor structure as in a traditional DRAM. The vertical structure contributes greatly to a decrease in cell dimension. The main concept of the NEM switch and capacitor can be applied to other memory devices as well. © 2005 IEEE.