Analytic model for turn off in the silicon-on-insulator LIGBT

Lateral insulated gate bipolar transistors (LIGBTs) in silicon-on-insulator (SOI) show a unique turn off characteristic when compared to junction-isolated RESURF LIGBTs or vertical IGBTs. The turn off characteristic shows an extended `terrace' where, after the initial fast transient characteristic of IGBTs due to the loss of the electron current, the current stays almost at the same value for an extended period of time, before suddenly dropping to zero. In this paper, we show that this terrace arises because there is a value of LIGBT current during switch off where the rate of expansion of the depletion region with respect to the anode current is infinite. Once this level of anode current is approached, the depletion region starts to expand very rapidly, and is only stopped when it reaches the n-type buffer layer surrounding the anode. Once this happens, the current rapidly drops to zero. A quasi-static analytic model is derived to explain this behaviour. The analytically modelled turn off characteristic agrees well with that found by numerical simulation.

Analytical model for the 3D-RESURF effect

This paper presents an analytical model for the determination of the basic breakdown properties of three-dimensional (3D)-RESURF/CoolMOS/super junction type structures. To account for the two-dimensional (2D) effect of the 3D-RESURF action, 2D models of the electric field distribution are developed. Based on these, expressions are derived for the breakdown voltage as a function of doping concentration and physical dimensions. In addition to cases where the drift regions are fully depleted, the model developed is also applicable to situations involving drift regions which are almost depleted. Accuracy of the analytical approach is verified by comparison with numerical results obtained from the MEDICI device simulator.

Millisecond processing beyond chip technology: From electronics to photonics

There is a clear and increasing interest in short time annealing processing far below one second, i.e. the lower limit of Rapid Thermal Processing (RTP) called spike annealing. This was driven by the need of suppressing the so-called Transient Enhanced Diffusion in advanced boronimplanted shallow pn-junctions in silicon technology. Meanwhile the interest in flash lamp annealing (FLA) in the millisecond range spread out into other fields related to silicon technology and beyond. This paper reports on recent experiments regarding shallow junction engineering in germanium, annealing of ITO layers on glass and plastic foil to form an conductive layer as well as investigations which we did during the last years in the field of wide band gap semiconductor materials (SiC, ZnO). A more common feature evolving from our work was related to the modeling of wafer stress during millisecond thermal processing with flash lamps. Finally recent achievements in the field of silicon-based light emission basing on Metal-Oxide-Semiconductor Light Emitting Devices will be reported. © 2007 IEEE.

Advanced thermal processing of semiconductor materials in the msec-range

This paper reviews the advances that flash lamp annealing brings to the processing of the most frequently used semiconductor materials, namely silicon and silicon carbide, thus enabling the fabrication of novel microelectronic structures and materials. The paper describes how such developments can translate into important practical applications leading to a wide range of technological benefits. Opportunities in ultra-shallow junction formation, heteroepitaxial growth of thin films of cubic silicon carbide on silicon, and crystallization of amorphous silicon films, along with the technical reasons for using flash lamp annealing are discussed in the context of state-of-the-art materials processing. © 2005 IEEE.

Spice modelling of the superjunction IGBT

This paper presents a SPICE model of the SuperJunction Insulated Gate Bipolar Transistor (SJIGBT) [1]. SPICE simulation results are in good agreement with the DESSIS simulation results under DC conditions. This model consists of an intrinsic MOSFET and a parallel combination of a wide and a narrow base pnp BJTs. A parasitic JFET is also included to account for the restricted current flow between two adjacent p-wells. In addition the JFET component also models the additional depletion region caused by the transverse junction at the upper side of the n-drift region where the current is mainly transported via majority carriers.

Strong plasmonic enhancement of photovoltage in graphene

From the wide spectrum of potential applications of graphene, ranging from transistors and chemical sensors to nanoelectromechanical devices and composites, the field of photonics and optoelectronics is believed to be one of the most promising. Indeed, graphene's suitability for high-speed photodetection was demonstrated in an optical communication link operating at 10 Gbit s 1. However, the low responsivity of graphene-based photodetectors compared with traditional III-V-based ones is a potential drawback. Here we show that, by combining graphene with plasmonic nanostructures, the efficiency of graphene-based photodetectors can be increased by up to 20 times, because of efficient field concentration in the area of a p-n junction. Additionally, wavelength and polarization selectivity can be achieved by employing nanostructures of different geometries. © 2011 Macmillan Publishers Limited. All rights reserved.

Investigation into IGBT dV/dt during turn-off and its temperature dependence

In many power converter applications, particularly those with high variable loads, such as traction and wind power, condition monitoring of the power semiconductor devices in the converter is considered desirable. Monitoring the device junction temperature in such converters is an essential part of this process. In this paper, a method for measuring the insulated gate bipolar transistor (IGBT) junction temperature using the collector voltage dV/dt at turn-OFF is outlined. A theoretical closed-form expression for the dV/dt at turn-OFF is derived, closely agreeing with experimental measurements. The role of dV/dt in dynamic avalanche in high-voltage IGBTs is also discussed. Finally, the implications of the temperature dependence of the dV/dt are discussed, including implementation of such a temperature measurement technique. © 2006 IEEE.

Performance prediction of graphene nanoribbon and carbon nanotube transistors

Carbon nanotubes (CNTs) and graphene nanoribbons (GNRs) field-effect transistor (FET) can be the basis for a quasi-one- dimensional (Q1D) transistor technology. Recent experiments show that the on-off ratio for GNR devices can be improved to level exploration of transistor action is justified. Here we use the tight-binding energy dipersion approximation, to assess the performance of semiconducting CNT and GNR is qualitatively in terms of drain current drive strength, bandgap and density of states for a specified device. By reducing the maximum conductance 4e2/h by half, we observed that our model has a particularly good fit with 50 nm channel single walled carbon nanotube (SWCNT) experimental data. Given the same bandgap, CNTs outperform GNRs due to valley degeneracy. Nevertheless, the variation of the device contacts will decide which transistor will exhibit better conductivity and thus higher ON currents. © 2011 American Institute of Physics.

Low temperature (< 100 °c) deposited P-type cuprous oxide thin films: Importance of controlled oxygen and deposition energy

With the emergence of transparent electronics, there has been considerable advancement in n-type transparent semiconducting oxide (TSO) materials, such as ZnO, InGaZnO, and InSnO. Comparatively, the availability of p-type TSO materials is more scarce and the available materials are less mature. The development of p-type semiconductors is one of the key technologies needed to push transparent electronics and systems to the next frontier, particularly for implementing p-n junctions for solar cells and p-type transistors for complementary logic/circuits applications. Cuprous oxide (Cu2O) is one of the most promising candidates for p-type TSO materials. This paper reports the deposition of Cu2O thin films without substrate heating using a high deposition rate reactive sputtering technique, called high target utilisation sputtering (HiTUS). This technique allows independent control of the remote plasma density and the ion energy, thus providing finer control of the film properties and microstructure as well as reducing film stress. The effect of deposition parameters, including oxygen flow rate, plasma power and target power, on the properties of Cu2O films are reported. It is known from previously published work that the formation of pure Cu2O film is often difficult, due to the more ready formation or co-formation of cupric oxide (CuO). From our investigation, we established two key concurrent criteria needed for attaining Cu2O thin films (as opposed to CuO or mixed phase CuO/Cu2O films). First, the oxygen flow rate must be kept low to avoid over-oxidation of Cu2O to CuO and to ensure a non-oxidised/non-poisoned metallic copper target in the reactive sputtering environment. Secondly, the energy of the sputtered copper species must be kept low as higher reaction energy tends to favour the formation of CuO. The unique design of the HiTUS system enables the provision of a high density of low energy sputtered copper radicals/ions, and when combined with a controlled amount of oxygen, can produce good quality p-type transparent Cu2O films with electrical resistivity ranging from 102 to 104 Ω-cm, hole mobility of 1-10 cm2/V-s, and optical band-gap of 2.0-2.6 eV. These material properties make this low temperature deposited HiTUS Cu 2O film suitable for fabrication of p-type metal oxide thin film transistors. Furthermore, the capability to deposit Cu2O films with low film stress at low temperatures on plastic substrates renders this approach favourable for fabrication of flexible p-n junction solar cells. © 2011 Elsevier B.V. All rights reserved.

Channel selective tunnelling through a nanographene assembly.

We report selective tunnelling through a nanographene intermolecular tunnel junction achieved via scanning tunnelling microscope tip functionalization with hexa-peri-hexabenzocoronene (HBC) molecules. This leads to an offset in the alignment between the energy levels of the tip and the molecular assembly, resulting in the imaging of a variety of distinct charge density patterns in the HBC assembly, not attainable using a bare metallic tip. Different tunnelling channels can be selected by the application of an electric field in the tunnelling junction, which changes the condition of the HBC on the tip. Density functional theory-based calculations relate the imaged HBC patterns to the calculated molecular orbitals at certain energy levels. These patterns bear a close resemblance to the π-orbital states of the HBC molecule calculated at the relevant energy levels, mainly below the Fermi energy of HBC. This correlation demonstrates the ability of an HBC functionalized tip as regards accessing an energy range that is restricted to the usual operating bias range around the Fermi energy with a normal metallic tip at room temperature. Apart from relating to molecular orbitals, some patterns could also be described in association with the Clar aromatic sextet formula. Our observations may help pave the way towards the possibility of controlling charge transport between organic interfaces.

Transient electrothermal simulation of power semiconductor devices

In this paper, a new thermal model based on the Fourier series solution of heat conduction equation has been introduced in detail. 1-D and 2-D Fourier series thermal models have been programmed in MATLAB/Simulink. Compared with the traditional finite-difference thermal model and equivalent RC thermal network, the new thermal model can provide high simulation speed with high accuracy, which has been proved to be more favorable in dynamic thermal characterization on power semiconductor switches. The complete electrothermal simulation models of insulated gate bipolar transistor (IGBT) and power diodes under inductive load switching condition have been successfully implemented in MATLAB/Simulink. The experimental results on IGBT and power diodes with clamped inductive load switching tests have verified the new electrothermal simulation model. The advantage of Fourier series thermal model over widely used equivalent RC thermal network in dynamic thermal characterization has also been validated by the measured junction temperature.© 2010 IEEE.

Dynamic characterisation and longitudinal strength of swaged joints

Swaging is a cold working process involving plastic deformation of the work piece to change its shape. A swaged joint is a connection between two components whereby a swaging tool induces plastic deformation of the components at their junction to effectively bind them together. This is commonly used when welding or other standard joining techniques are not viable. Swaged joints can be found for example, in nuclear fuel assemblies to connect the edges of thin rectangular plates to a supporting structure or frame. The aim of this work is to find a model to describe the vibrational behaviour of a swaged joint and to estimate its strength in resisting a longitudinally applied load. The finite element method and various experimental rigs were used in order to find relationships between the natural frequencies of the plate, the joint stiffness and the force required to shift the plate against the restraining action of the swage connection. It is found that a swaged joint is dynamically equivalent to a simple support with the rotation elastically restrained and a small stiffness is enough to resist an important load. © 2011 Elsevier Ltd. All rights reserved.

Conduction bottleneck in silicon nanochain single electron transistors operating at room temperature

Single electron transistors are fabricated on single Si nanochains, synthesised by thermal evaporation of SiO solid sources. The nanochains consist of one-dimensional arrays of ~10nm Si nanocrystals, separated by SiO 2 regions. At 300 K, strong Coulomb staircases are seen in the drain-source current-voltage (I ds-V ds) characteristics, and single-electron oscillations are seen in the drain-source current-gate voltage (I ds-V ds) characteristics. From 300-20 K, a large increase in the Coulomb blockade region is observed. The characteristics are explained using singleelectron Monte Carlo simulation, where an inhomogeneous multiple tunnel junction represents a nanochain. Any reduction in capacitance at a nanocrystal well within the nanochain creates a conduction " bottleneck", suppressing current at low voltage and improving the Coulomb staircase. The single-electron charging energy at such an island can be very high, ~20k BT at 300 K. © 2012 The Japan Society of Applied Physics.

Two is better than one: Distinct roles for familiarity and recollection in retrieving palimpsest memories

Storing a new pattern in a palimpsest memory system comes at the cost of interfering with the memory traces of previously stored items. Knowing the age of a pattern thus becomes critical for recalling it faithfully. This implies that there should be a tight coupling between estimates of age, as a form of familiarity, and the neural dynamics of recollection, something which current theories omit. Using a normative model of autoassociative memory, we show that a dual memory system, consisting of two interacting modules for familiarity and recollection, has best performance for both recollection and recognition. This finding provides a new window onto actively contentious psychological and neural aspects of recognition memory.

Cortical thickness mapping to identify focal osteoporosis in patients with hip fracture.

BACKGROUND: Individuals with osteoporosis are predisposed to hip fracture during trips, stumbles or falls, but half of all hip fractures occur in those without generalised osteoporosis. By analysing ordinary clinical CT scans using a novel cortical thickness mapping technique, we discovered patches of markedly thinner bone at fracture-prone regions in the femurs of women with acute hip fracture compared with controls. METHODS: We analysed CT scans from 75 female volunteers with acute fracture and 75 age- and sex-matched controls. We classified the fracture location as femoral neck or trochanteric before creating bone thickness maps of the outer 'cortical' shell of the intact contra-lateral hip. After registration of each bone to an average femur shape and statistical parametric mapping, we were able to visualise and quantify statistically significant foci of thinner cortical bone associated with each fracture type, assuming good symmetry of bone structure between the intact and fractured hip. The technique allowed us to pinpoint systematic differences and display the results on a 3D average femur shape model. FINDINGS: The cortex was generally thinner in femoral neck fracture cases than controls. More striking were several discrete patches of statistically significant thinner bone of up to 30%, which coincided with common sites of fracture initiation (femoral neck or trochanteric). INTERPRETATION: Femoral neck fracture patients had a thumbnail-sized patch of focal osteoporosis at the upper head-neck junction. This region coincided with a weak part of the femur, prone to both spontaneous 'tensile' fractures of the femoral neck, and as a site of crack initiation when falling sideways. Current hip fracture prevention strategies are based on case finding: they involve clinical risk factor estimation to determine the need for single-plane bone density measurement within a standard region of interest (ROI) of the femoral neck. The precise sites of focal osteoporosis that we have identified are overlooked by current 2D bone densitometry methods.