Tetrahedral amorphous carbon-silicon heterojunction band energy offsets

Non-hydrogenated tetrahedral amorphous carbon (ta-C) has shown superior field emission characteristics. The understanding of the emission mechanism has been hindered by the lack of any directly measured data on the band offsets between ta-C and Si. In this paper results from direct in situ X-ray photoemission spectroscopy (XPS) measurements of the band-offset between ta-C and Si are reported. The measurements were carried out using a filtered cathodic vacuum arc (FCVA) deposition system attached directly to an ultra-high vacuum (UHV) XPS chamber via a load lock chamber. Repeated XPS measurements were carried out after monolayer depositions on in situ cleaned Si substrates. The total film thickness for each set of measurements was approximately 5 nm. Analysis of the data from undoped ta-C on n and p Si show the unexpected result that the conduction band barrier between Si and ta-C remains around 1.0 eV, but that the valence band barrier changes from 0.7 to 0.0 eV. The band line up derived from these barriers suggests that the Fermi level in the ta-C lies 0.3 eV above the valence band on both p and n+Si. The heterojunction barriers when ta-C is doped with nitrogen are also presented. The implications of the heterojunction energy barrier heights for field emission from ta-C are discussed.

Defined etching of carbon-diamond films on silicon using an oxygen plasma with titanium masking

A technique for pattern transfer onto carbon-diamond films deposited by radio-frequency plasma-enhanced chemical vapour deposition is reported. Such a technique involves standard photolithography processes and reactive ion etching by oxygen and is compatible with present day microelectronic technology. The patterns transferred are well defined with very good resolution. © 1992.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.