Application of electron beams in thermal processing of semiconductor materials and devices

Rapid and effective thermal processing methods using electron beams are described in this paper. Heating times ranging from a fraction of a second to several seconds and temperatures up to 1400°C are attainable. Applications such as the annealing of ion implanted material, both without significant dopant diffusion and with highly controlled diffusion of impurities, are described. The technique has been used successfully to activate source/drain regions for fine geometry NMOS transistors. It is shown that electron beams can produce localised heating of semiconductor substrates and a resolution of approximately 1 μm has been achieved. Electron beam heating has been applied to improving the crystalline quality of silicon-on sapphire used in CMOS device fabrication. Silicon layers with defect levels approaching bulk material have been obtained. Finally, the combination of isothermal and selective annealing is shown to have application in recrystallisation of polysilicon films on an insulating layer. The approach provides the opportunity of producing a silicon-on-insulator substrate with improved crystalline quality compared to silicon-on-sapphire at a potentially lower cost. It is suggested that rapid heating methods are expected to provide a real alternative to conventional furnace processing of semiconductor devices in the development of fabrication technology. © 1984 Benn electronics Publications Ltd, Luton.

Performance of CMOS Devices in Silicon-on-Sapphire Films After Solid-Phase Epitaxial Growth With Rapid Electron-Beam Heating

The crystal quality of 0.3-μm-thick as-grown epitaxial silicon-on-sapphire (SOS) was improved using solid-phase epitaxy (SPE) by implantation with silicon to 1015 ions/cm2 at 175 keV and rapid annealing using electron-beam heating, n-channel and p-channel transistormobilities increased by 31 and 19 percent, respectively, and a reduction in ring-oscillator stage delay confirmed that crystal defects near the upper silicon surface had been removed. Leakage in n-channel transistors was not significantly affected by the regrowth process but for p-channel transistors back-channel leakage was considerably greater than for the control devices. This is attributed to aluminum released by damage to the sapphire during silicon implantation. © 1985 IEEE

REGROWTH RATES OF AMORPHOUS LAYERS IN SILICON-ON-SAPPHIRE FILMS.

The rate and direction of regrowth of amorphous layers, created by self-implantation, in silicon-on-sapphire (SOS) have been studied using time resolved reflectivity (TRR) experiments performed simultaneously at two wavelengths. Regrowth of an amorphous layer towards the surface was observed in specimens implanted with 3 multiplied by (times) 10**1**5Si** plus /cm**2 at 50keV and regrowth of a buried amorphous layer, from a surface seed towards the sapphire, was observed in specimens implanted with 1 multiplied by (times) 10**1**5Si** plus /cm**2 at 175keV. Rapid isothermal heating to regrow the layers was performed in an electron beam annealing system. The combination of 514. 5nm and 632. 8nm wavelengths was found to be particularly useful for TRR studies since the high absorption in amorphous silicon, at the shorter wavelength, means that the TRR trace is not complicated by reflection from the silicon-sapphire interface until regrowth is nearly complete.

Comments on "micro-scale abrasive wear testing of PVD coatings on curved substrates"

Previously published expressions for the wear volume in the micro-scale abrasion test for curved specimen surfaces (K.L. Rutherford and I.M. Hutchings, Tribology Letters 2 (1996) 1-11) were based upon erroneous assumptions about the wear-scar geometry. Accurate volumes have now been computed, and the errors in the use of the original analytical equations are shown to be negligibly small (<0.5% error) for all practical cases. © J.C. Baltzer AG, Science Publishers.

Amorphous silicon display backplanes on plastic substrates

Amorphous silicon thin-film transistors and pixel driver circuits for organic light-emitting diode displays have been fabricated on plastic substrates. Pixel circuits demonstrate sufficient current delivery and long-term stable operation. © 2005 IEEE.

Calculating transport AC losses in stacks of high temperature superconductor coated conductors with magnetic substrates using FEM

In this paper, the authors investigate the electromagnetic properties of stacks of high temperature superconductor (HTS) coated conductors with a particular focus on calculating the total transport AC loss. The cross-section of superconducting cables and coils is often modeled as a two-dimensional stack of coated conductors, and these stacks can be used to estimate the AC loss of a practical device. This paper uses a symmetric two dimensional (2D) finite element model based on the H formulation, and a detailed investigation into the effects of a magnetic substrate on the transport AC loss of a stack is presented. The number of coated conductors in each stack is varied from 1 to 150, and three types of substrate are compared: non-magnetic weakly magnetic and strongly magnetic. The non-magnetic substrate model is comparable with results from existing models for the limiting cases of a single tape (Norris) and an infinite stack (Clem). The presence of a magnetic substrate increases the total AC loss of the stack, due to an increased localized magnetic flux density, and the stronger the magnetic material, the further the flux penetrates into the stack overall. The AC loss is calculated for certain tapes within the stack, and the differences and similarities between the losses throughout the stack are explained using the magnetic flux penetration and current density distributions in those tapes. The ferromagnetic loss of the substrate itself is found to be negligible in most cases, except for small magnitudes of current. Applying these findings to practical applications, where AC transport current is involved, superconducting coils should be wound where possible using coated conductors with a non-magnetic substrate to reduce the total AC loss in the coil. © 2011 Elsevier B.V. All rights reserved.

High efficiency liquid crystal lasers giving "white light" emission from arrays and flexible substrates

The self-organization of the helical structure of chiral nematic liquid crystals combined with their sensitivity to electric fields makes them particularly interesting for low-threshold, wavelength tunable laser devices. We have studied these organic lasers in detail, ranging from the influence specific macroscopic properties, such as birefringence and order parameter, have on the output characteristics, to practical systems in the form of two-dimensional arrays, double-pass geometries and paintable lasers. Furthermore, even though chiral nematics are responsive to electric fields there is no facile means by which the helix periodicity can be adjusted, thereby allowing laser wavelength tuning, without adversely affecting the optical quality of the resonator. Therefore, in addition to studying the liquid crystal lasers, we have focused on finding a novel method with which to alter the periodicity of a chiral nematic using electric fields without inducing defects and degrading the optical quality factor of the resonator. This paper presents an overview of our research, describing (i) the correlation between laser output and material properties,(ii) the importance of the gain medium,(iii) multicolor laser arrays, and (iv) high slope efficiency (>60%) silicon back-plane devices. Overall we conclude that these materials have great potential for use in versatile organic laser systems.

High-efficiency InGaN/GaN quantum well structures on large area silicon substrates

The growth techniques which have enabled the realization of InGaN-based multi-quantum-well (MQW) structures with high internal quantum efficiencies (IQE) on 150mm (6-in.) silicon substrates are reviewed. InGaN/GaN MQWs are deposited onto GaN templates on large-area (111) silicon substrates, using AlGaN strain-mediating interlayers to inhibit thermal-induced cracking and wafer-bowing, and using a SiN x interlayer to reduce threading dislocation densities in the active region of the MQW structure. MQWs with high IQE approaching 60% have been demonstrated. Atomic resolution electron microscopy and EELS analysis have been used to study the nature of the important interface between the Si(111) substrate and the AlN nucleation layer. We demonstrate an amorphous SiN x interlayer at the interface about 2nm wide, which does not, however, prevent good epitaxy of the AlN on the Si(111) substrate. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.