Silicon on insulator thermodiode with extremely wide working temperature range

This paper presents for the first time the performance of a silicon-on-insulator (SOI) p-n thermodiode, which can operate in an extremely wide temperature range of 200°C to 700°C while maintaining its linearity. The thermodiode is embedded in a thin dielectric membrane underneath a tungsten microheater, which allows the diode characterization at very high temperature (> 800°C). The effect of the junction area (Aj) on the thermodiode linearity, sensitivity and self-heating is experimentally and theoretically investigated. Results on the long-term diode stability at high temperature are also reported. © 2013 IEEE.

High-resolution strain sensing on steel by Silicon-On-Insulator flexural resonators fabricated with chip-level vacuum packaging

This paper reports on the fabrication and characterization of high-resolution strain sensors for steel based on Silicon On Insulator flexural resonators manufactured with chip-level LPCVD vacuum packaging. The sensors present high sensitivity (120 Hz/μ), very high resolution (4 n), low drift, and near-perfect reversibility in bending tests performed in both tensile and compressive strain regimes. © 2013 IEEE.

Partial soi power LDMOS with a variable low-kappa; Dielectric buried layer and a buried P layer

A power LDMOS on partial silicon on insulator (PSOI) with a variable low-κ dielectric (VLKD) buried layer and a buried p (BP) layer is proposed (VLKD BPSOI). At a low κ value, the electric field strength in the buried dielectric (EI) is enhanced, and a Si window makes the substrate share the vertical voltage drop, leading to a high vertical breakdown voltage (BV). Moreover, three interface field peaks are introduced by the BP, the Si window, and the VLKD, which modulate the fields in the SOI layer, the VLKD layer, and the substrate; consequently, a high BV is obtained. Furthermore, the BP reduces the specific on-resistance (Ron), and the Si window alleviates the self-heating effect (SHE). The BV for VLKD BPSOI is enhanced by 34.5%, and Ron is decreased by 26.6%, compared with those for the conventional PSOI, and VLKD BPSOI also maintains a low SHE. © 2006 IEEE.

Multi-field simulations and characterization of CMOS-MEMS high-temperature smart gas sensors based on SOI technology

This paper describes multiple field-coupled simulations and device characterization of fully CMOS-MEMS-compatible smart gas sensors. The sensor structure is designated for gas/vapour detection at high temperatures (>300 °C) with low power consumption, high sensitivity and competent mechanic robustness employing the silicon-on-insulator (SOI) wafer technology, CMOS process and micromachining techniques. The smart gas sensor features micro-heaters using p-type MOSFETs or polysilicon resistors and differentially transducing circuits for in situ temperature measurement. Physical models and 3D electro-thermo-mechanical simulations of the SOI micro-hotplate induced by Joule, self-heating, mechanic stress and piezoresistive effects are provided. The electro-thermal effect initiates and thus affects electronic and mechanical characteristics of the sensor devices at high temperatures. Experiments on variation and characterization of micro-heater resistance, power consumption, thermal imaging, deformation interferometry and dynamic thermal response of the SOI micro-hotplate have been presented and discussed. The full integration of the smart gas sensor with automatically temperature-reading ICs demonstrates the lowest power consumption of 57 mW at 300 °C and fast thermal response of 10 ms. © 2008 IOP Publishing Ltd.

A bulk acoustic mode single-crystal silicon microresonator with a high-quality factor

This paper details a bulk acoustic mode resonator fabricated in single-crystal silicon with a quality factor of 15 000 in air, and over a million below 10 mTorr at a resonant frequency of 2.18 MHz. The resonator is a square plate that is excited in the square-extensional mode and has been fabricated in a commercial foundry silicon-on-insulator (SOI) MEMS process through MEMSCAP. This paper also presents a simple method of extracting resonator parameters from raw measurements heavily buried in electrical feedthrough. Its accuracy has been demonstrated through a comparison between extracted motional resistance values measured at different voltage biases and those predicted from an analytical model. Finally, a method of substantially cancelling electrical feedthrough through system-level electronic implementation is also introduced. © 2008 IOP Publishing Ltd.

Square wine glass mode resonator with quality factor of 4 million

We report on the experimental characterization of a single crystal silicon square-plate microresonator. The resonator is excited in the square wine glass (SWG) mode at a mechanical resonance frequency of 2.065 MHz. The resonator displays quality factor of 9660 in air and an ultra-high quality factor of Q = 4.05 × 106 in 12 mtorr vacuum. The SWG mode may be described as a square plate that contracts along one axis in the fabrication plane, while simultaneously extending along an orthogonal axis in the same plane. The resonant structure is addressed in a 2-terminal configuration by utilizing equal and opposite drive polarities on surrounding capacitor electrodes, thereby decreasing the motional resistance of the resonator. The resonant micromechanical device has been fabricated in a commercial silicon-on-insulator process through the MEMSCAP foundry utilising a minimum electrostatic gap of 2 μm. © 2008 IEEE.

Advantages of top-gate, high-k dielectric carbon nanotube field-effect transistors

The subthreshold slope, transconductance, threshold voltage, and hysteresis of a carbon nanotube field-effect transistor (CNT FET) were examined as its configuration was changed from bottom-gate exposed channel, bottom-gate covered channel to top-gate FET. An individual single wall CNT was grown by chemical vapor deposition and its gate configuration was changed while determining its transistor characteristics to ensure that the measurements were not a function of different chirality or diameter CNTs. The bottom-gate exposed CNT FET utilized 900 nm SiO2 as the gate insulator. This CNT FET was then covered with TiO2 to form the bottom-gate covered channel CNT FET. Finally, the top-gate CNT FET was fabricated and the device utilized TiO 2 (K ∼ 80, equivalent oxide thickness=0.25 nm) as the gate insulator. Of the three configurations investigated, the top-gate device exhibited best subthreshold slope (67-70 mV/dec), highest transconductance (1.3 μS), and negligible hysteresis in terms of threshold voltage shift. © 2006 American Institute of Physics.

Self-aligned, gated arrays of individual nanotube and nanowire emitters

We demonstrate the production of integrated-gate nanocathodes which have a single carbon nanotube or silicon nanowire/whisker per gate aperture. The fabrication is based on a technologically scalable, self-alignment process in which a single lithographic step is used to define the gate, insulator, and emitter. The nanotube-based gated nanocathode array has a low turn-on voltage of 25 V and a peak current of 5 μA at 46 V, with a gate current of 10 nA (i.e., 99% transparency). These low operating voltage cathodes are potentially useful as electron sources for field emission displays or miniaturizing electron-based instrumentation.

Study of lateral mode SOI-MEMS resonators for reduced anchor loss

MEMS resonators fabricated in silicon-on-insulator (SOI) technology must be clamped to the substrate via anchoring stems connected either from within the resonator or through the sides, with the side-clamped solution often employed due to manufacturing constraints. This paper examines the effect of two types of commonly used side-clamped, anchoring-stem geometries on the quality factor of three different laterally-driven resonator topologies. This study employs an analytical framework which considers the relative distribution of strain energies between the resonating body and clamping stems. The ratios of the strain energies are computed using ANSYS FEA and used to provide an indicator of the expected anchor-limited quality factors. Three MEMS resonator topologies have been fabricated and characterized in moderate vacuum. The associated measured quality factors are compared against the computed strain energy ratios, and the trends are shown to agree well with the experimental data. © 2011 IOP Publishing Ltd.

More oomph

An ingenious new CMOS-compatible process which promises to significantly improve the performance of power devices is discussed. A novel power device concept based on the use of high voltage regions suspended on thin semiconductor/dielectric membranes is reported. The membrane power devices are manufactured in a fully-CMOS compatible silicon-on-insulator (SOI) process followed by a bulk etching step and subsequent back-passivation. The concept is applicable to a class of high voltage devices such as LDMOSFETs, diodes, LIGBTs and superjunctions.

Application of electron beams in thermal processing of semiconductor materials and devices

Rapid and effective thermal processing methods using electron beams are described in this paper. Heating times ranging from a fraction of a second to several seconds and temperatures up to 1400°C are attainable. Applications such as the annealing of ion implanted material, both without significant dopant diffusion and with highly controlled diffusion of impurities, are described. The technique has been used successfully to activate source/drain regions for fine geometry NMOS transistors. It is shown that electron beams can produce localised heating of semiconductor substrates and a resolution of approximately 1 μm has been achieved. Electron beam heating has been applied to improving the crystalline quality of silicon-on sapphire used in CMOS device fabrication. Silicon layers with defect levels approaching bulk material have been obtained. Finally, the combination of isothermal and selective annealing is shown to have application in recrystallisation of polysilicon films on an insulating layer. The approach provides the opportunity of producing a silicon-on-insulator substrate with improved crystalline quality compared to silicon-on-sapphire at a potentially lower cost. It is suggested that rapid heating methods are expected to provide a real alternative to conventional furnace processing of semiconductor devices in the development of fabrication technology. © 1984 Benn electronics Publications Ltd, Luton.