High power laser with integrated lens using focused ion beam etching

In this study, a collimating lens is introduced at the output facet of a tapered waveguide laser to compensate for the divergence of the optical mode. The collimating lens is shown to enhance the laser efficiency while simultaneously reducing the far field divergence.

Significant improvements in optical power budgets of real-time optical OFDM PON systems.

Based on a comprehensive theoretical optical orthogonal frequency division multiplexing (OOFDM) system model rigorously verified by comparing numerical results with end-to-end real-time experimental measurements at 11.25Gb/s, detailed explorations are undertaken, for the first time, of the impacts of various physical factors on the OOFDM system performance over directly modulated DFB laser (DML)-based, intensity modulation and direct detection (IMDD), single-mode fibre (SMF) systems without in-line optical amplification and chromatic dispersion compensation. It is shown that the low extinction ratio (ER) of the DML modulated OOFDM signal is the predominant factor limiting the maximum achievable optical power budget, and the subcarrier intermixing effect associated with square-law photon detection in the receiver reduces the optical power budget by at least 1dB. Results also indicate that, immediately after the DML in the transmitter, the insertion of a 0.02nm bandwidth optical Gaussian bandpass filter with a 0.01nm wavelength offset with respect to the optical carrier wavelength can enhance the OOFDM signal ER by approximately 1.24dB, thus resulting in a 7dB optical power budget improvement at a total channel BER of 1 × 10(-3).

A 660MHz ZVS DC-DC converter using gate-driver charge-recycling in 0.18μm CMOS with an integrated output filter

The design and manufacture of a prototype chip level power supply is described, with both simulated and experimental results. Of particular interest is the inclusion of a fully integrated on-chip LC filter. A high switching frequency of 660MHz and the design of a device drive circuit reduce losses by supply stacking, low-swing signaling and charge recycling. The paper demonstrates that a chip level converter operating at high frequency can be built and shows how this can be achieved, using zero voltage switching techniques similar to those commonly used in larger converters. Both simulations and experimental data from a fabricated circuit in 0.18μm CMOS are included. The circuit converts 2.2V to 0.75∼1.0V at ∼55mA. ©2008 IEEE.

Electronic load interface for improving PV dual-converter system operational margin

An electronic load interface (ELI) for improving the operational margin of a photovoltaic (PV) dual-converter system under dynamic conditions is presented. The ELI - based on a modified buck-boost converter - interfaces the output of the converters and the load system. It improves the operational margin of the PV dual-converter system by extending the conditions under which the dual-converter system operates at the maximum power point. The ELI is activated as and when needed, so as minimise system losses. By employing the ELI, utilisation and efficiency of a PV dual-converter system increases. In general, the concept of the ELI can be applied to multi-converter PV systems - such as multi-converter inverters, and multi-converter DC-DC converter systems - for performance and efficiency improvement. © 2013 The Institution of Engineering and Technology.

Gate commutated thyristor with voltage independent maximum controllable current

In this letter, we use a novel 3-D model, earlier calibrated with experimental results on standard gate commutated thyristors (GCTs), with the aim to explain the physics behind the high-power technology (HPT) GCT, to investigate what impact this design would have on 24 mm diameter GCTs, and to clarify the mechanisms that limit safe switching at different dc-link voltages. The 3-D simulation results show that the HPT design can increase the maximum controllable current in 24 mm diameter devices beyond the realm of GCT switching, known as the hard-drive limit. It is proposed that the maximum controllable current becomes independent of the dc-link voltage for the complete range of operating voltage. © 1980-2012 IEEE.

A 40 Gb/s optical bus for optical backplane interconnections

Optical technologies have received large interest in recent years for use in board-level interconnects. Polymer multimode waveguides in particular, constitute a promising technology for high-capacity optical backplanes as they can be cost-effectively integrated onto conventional printed circuit boards (PCBs). This paper presents the first optical backplane demonstrator based on the use of PCB-integrated polymer multimode waveguides and a regenerative shared bus architecture. The backplane demonstrator is formed with commercially-available low-cost electronic and photonic components onto conventional FR4 substrates and comprises two opto-electronic (OE) bus modules interconnected via a prototype regenerator unit. The system enables interconnection between the connected cards over four optical channels, each operating at 10 Gb/s. Bus extension is achieved by cascading OE bus modules via 3R regenerator units, overcoming therefore the inherent limitation of optical bus topologies in the maximum number of cards that can be connected to the bus. Details of the design, fabrication, and assembly of the different parts of this optical bus backplane are presented and related optical and data transmission characterisation studies are reported. The optical layer of the OE bus modules comprises a four-channel three-card waveguide layout that is compatible with VCSEL/PD arrays and ribbon fibres. All on-board optical paths exhibit insertion losses below 13 dB and intra-channel crosstalk lower than -29 dB. The robustness of the signal distribution from the bus inputs to all respective bus output ports in the presence of input misalignment is demonstrated, while 1 dB input alignment tolerances of approximately ±10 μm are obtained. The electrical layer of the OE bus modules comprises the essential driving circuitry for 1×4 VCSEL and PD arrays and the corresponding control and power regulation circuits. The interface between the optical and electrical layers of the bus modules is achieved with simple OE connectors that enable end-fired optical coupling into and out of the on-board polymer waveguides. The backplane demonstrator achieves error-free (BER < 10-12) 10 Gb/s data transmission over each optical channel, enabling therefore, an aggregate interconnection capacity of 40 Gb/s between any connected cards. © 1983-2012 IEEE.