Theoretical and numerical investigation of SiC JFET and MOSFET at 6.5 kV

This paper presents a preliminary theoretical and numerical investigation of 4H-SiC JFET and MOSFET at 6.5 kV. To improve the on-state/breakdown performance of the JFET, buried layers in conjunction with a highly doped buffer layer have been used. Trench technology has been employed for the MOSFET. The devices were simulated and optimized using MEDICI[I] simulator. From the comparison between the two devices, it turns out that the JFET offers a better on-state/breakdown trade-off, while the trench MOSFET has the advantage of MOS-control.

Trench insulated gate bipolar transistor - a high power switching device

This paper presents a comprehensive theoretical study of the Trench Insulated Gate Bipolar Transistors (TIGBT). Specific physical and geometrical effects, such as the accumulation layer injection, increased channel density, increased channel charge and transversal electric field modulation are discussed. The potential advantages of the Trench IGBT over its conventional planar variant are highlighted. It is concluded that the Trench IGBT is one of the most promising structures in the area of high voltage MOS-controllable switching devices.

Use of a high-temperature superconducting coil for magnetic energy storage

A high temperature superconducting magnetic energy storage device (SMES) has been realised using a 350 m-long BSCCO tape wound as a pancake coil. The coil is mounted on a cryocooler allowing temperatures down to 17.2 K to be achieved. The temperature dependence of coil electrical resistance R(T) shows a superconducting transition at T 102.5 K. Measurements of the V(I) characteristics were performed at several temperatures between 17.2 K and 101.5 K to obtain the temperature dependence of the critical current (using a 1 νV/cm criterion). Critical currents were found to exceed 100 A for T < 30 K. An electronic DC-DC converter was built in order to control the energy flow in and out of the superconducting coil. The converter consists of a MOS transistor bridge switching at a 80 kHz frequency and controlled with standard Pulse Width Modulation (PWM) techniques. The system was tested using a 30 V squared wave power supply as bridge input voltage. The coil current, the bridge input and output voltages were recorded simultaneously. Using a 10 A setpoint current in the superconducting coil, the whole system (coil + DC-DC converter) can provide a stable output voltage showing uninterruptible power supply (UPS) capabilities over 1 s. © 2006 IOP Publishing Ltd.

Ni(Pt)-silicide contacts on CMOS devices: Impact of substrate nature and Pt concentration on the phase formation

Ni silicides used as contacts in source/drain and gate of advanced CMOS devices were analyzed by atom probe tomography (APT) at atomic scale. These measurements were performed on 45 nm nMOS after standard self-aligned silicide (salicide) process using Ni(5 at.% Pt) alloy. After the first annealing (RTA1), δ-Ni2Si was the only phase formed on gate and source/drain while, after the second annealing (RTA2), two different Ni silicides have been formed: NiSi on the gate and δ-Ni2Si on the source and drain. This difference between source/drain and gate regions in nMOS devices has been related to the Si substrate nature (poly or mono-crystalline) and to the size of the contact. In fact, NiSi seems to have difficulties to nucleate in the narrow source/drain contact on mono-crystalline Si. The results have been compared to analysis performed on 28 nm nMOS where the Pt concentration is higher (10 at.% Pt). In this case, θ-Ni2Si is the first phase to form after RTA1 and NiSi is then formed at the same time on source (or drain) and gate after RTA2. The absence of the formation of NiSi from δ-Ni 2Si/Si(1 0 0) interface compared to θ-Ni2Si/Si(1 0 0) interface could be related to the difference of the interface energies. The redistributions of As and Pt in different silicides and interfaces were measured and discussed. In particular, it has been evidenced that Pt redistributions obtained on both 45 and 28 nm MOS transistors correspond to respective Pt distributions measured on blanket wafers. © 2013 Elsevier B.V. All rights reserved.