Vertically oriented epitaxial germanium nanowires on silicon substrates using thin germanium buffer layers.

We demonstrate a method to realize vertically oriented Ge nanowires on Si(111) substrates. Ge nanowires were grown by chemical vapor deposition using Au nanoparticles to seed nanowire growth via a vapor-liquid-solid growth mechanism. Rapid oxidation of Si during Au nanoparticle application inhibits the growth of vertically oriented Ge nanowires directly on Si. The present method employs thin Ge buffer layers grown at low temperature less than 600 degrees C to circumvent the oxidation problem. By using a thin Ge buffer layer with root-mean-square roughness of approximately 2 nm, the yield of vertically oriented Ge nanowires is as high as 96.3%. This yield is comparable to that of homoepitaxial Ge nanowires. Furthermore, branched Ge nanowires could be successfully grown on these vertically oriented Ge nanowires by a secondary seeding technique. Since the buffer layers are grown under moderate conditions without any high temperature processing steps, this method has a wide process window highly suitable for Si-based microelectronics.

A hybrid density functional view of native vacancies in gallium nitride.

We investigated the transition energy levels of the vacancy defects in gallium nitride by means of a hybrid density functional theory approach (DFT). We show that, in contrast to predictions from a recent study on the level of purely local DFT, the inclusion of screened exchange stabilizes the triply positive charge state of the nitrogen vacancy for Fermi energies close to the valence band. On the other hand, the defect levels associated with the negative charge states of the nitrogen vacancy hybridize with the conduction band and turn out to be energetically unfavorable, except for high n-doping. For the gallium vacancy, the increased magnetic splitting between up-spin and down-spin bands due to stronger exchange interactions in sX-LDA pushes the defect levels deeper into the band gap and significantly increases the associated charge transition levels. Based on these results, we propose the ϵ(0| - 1) transition level as an alternative candidate for the yellow luminescence in GaN.

A discretized proportional base driver for Silicon Carbide Bipolar Junction Transistors

Silicon Carbide Bipolar Junction Transistors require a continuous base current in the on-state. This base current is usually made constant and is corresponding to the maximum collector current and maximum junction temperature that is foreseen in a certain application. In this paper, a discretized proportional base driver is proposed which will reduce, for the right application, the steady-state power consumption of the base driver. The operation of the proposed base driver has been verified experimentally, driving a 1200V/40A SiC BJT in a DC-DC boost converter. In order to determine the potential reduction of the power consumption of the base driver, a case with a dc-dc converter in an ideal electric vehicle driving the new European drive cycle has been investigated. It is found that the steady-state power consumption of the base driver can be reduced by approximately 63 %. The total reduction of the driver consumption is 2816 J during the drive cycle, which is slightly more than the total on-state losses for the SiC BJTs used in the converter. © 2013 IEEE.

Prospects of III-nitride optoelectronics grown on Si.

The use of III-nitride-based light-emitting diodes (LEDs) is now widespread in applications such as indicator lamps, display panels, backlighting for liquid-crystal display TVs and computer screens, traffic lights, etc. To meet the huge market demand and lower the manufacturing cost, the LED industry is moving fast from 2 inch to 4 inch and recently to 6 inch wafer sizes. Although Al2O3 (sapphire) and SiC remain the dominant substrate materials for the epitaxy of nitride LEDs, the use of large Si substrates attracts great interest because Si wafers are readily available in large diameters at low cost. In addition, such wafers are compatible with existing processing lines for 6 inch and larger wafers commonly used in the electronics industry. During the last decade, much exciting progress has been achieved in improving the performance of GaN-on-Si devices. In this contribution, the status and prospects of III-nitride optoelectronics grown on Si substrates are reviewed. The issues involved in the growth of GaN-based LED structures on Si and possible solutions are outlined, together with a brief introduction to some novel in situ and ex situ monitoring/characterization tools, which are especially useful for the growth of GaN-on-Si structures.

Silicon on insulator thermodiode with extremely wide working temperature range

This paper presents for the first time the performance of a silicon-on-insulator (SOI) p-n thermodiode, which can operate in an extremely wide temperature range of 200°C to 700°C while maintaining its linearity. The thermodiode is embedded in a thin dielectric membrane underneath a tungsten microheater, which allows the diode characterization at very high temperature (> 800°C). The effect of the junction area (Aj) on the thermodiode linearity, sensitivity and self-heating is experimentally and theoretically investigated. Results on the long-term diode stability at high temperature are also reported. © 2013 IEEE.

High-resolution strain sensing on steel by Silicon-On-Insulator flexural resonators fabricated with chip-level vacuum packaging

This paper reports on the fabrication and characterization of high-resolution strain sensors for steel based on Silicon On Insulator flexural resonators manufactured with chip-level LPCVD vacuum packaging. The sensors present high sensitivity (120 Hz/μ), very high resolution (4 n), low drift, and near-perfect reversibility in bending tests performed in both tensile and compressive strain regimes. © 2013 IEEE.

Model for quantum efficiency of guided mode plasmonic enhanced silicon Schottky detectors

Plasmonic enhanced Schottky detectors operating on the basis of the internal photoemission process are becoming an attractive choice for detecting photons with sub bandgap energy. Yet, the quantum efficiency of these detectors appears to be low compare to the more conventional detectors which are based on interband transitions in a semiconductor. Hereby we provide a theoretical model to predict the quantum efficiency of guided mode internal photoemission photodetector with focus on the platform of silicon plasmonics. The model is supported by numerical simulations and comparison to experimental results. Finally, we discuss approaches for further enhancement of the quantum efficiency.

Optimization of efficiency-loss figure of merit in carrier-depletion silicon Mach-Zehnder optical modulator.

In this paper we study the optimization of interleaved Mach-Zehnder silicon carrier depletion electro-optic modulator. Following the simulation results we demonstrate a phase shifter with the lowest figure of merit (modulation efficiency multiplied by the loss per unit length) 6.7 V-dB. This result was achieved by reducing the junction width to 200 nm along the phase-shifter and optimizing the doping levels of the PN junction for operation in nearly fully depleted mode. The demonstrated low FOM is the result of both low V(π)L of ~0.78 Vcm (at reverse bias of 1V), and low free carrier loss (~6.6 dB/cm for zero bias). Our simulation results indicate that additional improvement in performance may be achieved by further reducing the junction width followed by increasing the doping levels.

Waveguide based compact silicon Schottky photodetector with enhanced responsivity in the telecom spectral band.

We experimentally demonstrate an on-chip compact and simple to fabricate silicon Schottky photodetector for telecom wavelengths operating on the basis of internal photoemission process. The device is realized using CMOS compatible approach of local-oxidation of silicon, which enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. The photodetector demonstrates enhanced internal responsivity of 12.5mA/W for operation wavelength of 1.55µm corresponding to an internal quantum efficiency of 1%, about two orders of magnitude higher than our previously demonstrated results [22]. We attribute this improved detection efficiency to the presence of surface roughness at the boundary between the materials forming the Schottky contact. The combination of enhanced quantum efficiency together with a simple fabrication process provides a promising platform for the realization of all silicon photodetectors and their integration with other nanophotonic and nanoplasmonic structures towards the construction of monolithic silicon opto-electronic circuitry on-chip.

Plasmonic nanofocusing of light in an integrated silicon photonics platform.

The capability to focus electromagnetic energy at the nanoscale plays an important role in nanoscinece and nanotechnology. It allows enhancing light matter interactions at the nanoscale with applications related to nonlinear optics, light emission and light detection. It may also be used for enhancing resolution in microscopy, lithography and optical storage systems. Hereby we propose and experimentally demonstrate the nanoscale focusing of surface plasmons by constructing an integrated plasmonic/photonic on chip nanofocusing device in silicon platform. The device was tested directly by measuring the optical intensity along it using a near-field microscope. We found an order of magnitude enhancement of the intensity at the tip's apex. The spot size is estimated to be 50 nm. The demonstrated device may be used as a building block for "lab on a chip" systems and for enhancing light matter interactions at the apex of the tip.

Locally oxidized silicon surface-plasmon Schottky detector for telecom regime.

We experimentally demonstrate an on-chip nanoscale silicon surface-plasmon Schottky photodetector based on internal photoemission process and operating at telecom wavelengths. The device is fabricated using a self-aligned approach of local-oxidation of silicon (LOCOS) on silicon on insulator substrate, which provides compatibility with standard complementary metal-oxide semiconductor technology and enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. Additionally, LOCOS technique allows avoiding lateral misalignment between the silicon surface and the metal layer to form a nanoscale Schottky contact. The fabricated devices showed enhanced detection capability for shorter wavelengths that is attributed to increased probability of the internal photoemission process. We found the responsivity of the nanodetector to be 0.25 and 13.3 mA/W for incident optical wavelengths of 1.55 and 1.31 μm, respectively. The presented device can be integrated with other nanophotonic and nanoplasmonic structures for the realization of monolithic opto-electronic circuitry on-chip.

Demonstration of submicron square-like silicon waveguide using optimized LOCOS process.

We demonstrate the design, fabrication and experimental characterization of a submicron-scale silicon waveguide that is fabricated by local oxidation of silicon. The use of local oxidation process allows defining the waveguide geometry and obtaining smooth sidewalls. The process can be tuned to precisely control the shape and the dimensions of the waveguide. The fabricated waveguides are measured using near field scanning optical microscope at 1550 nm wavelength. These measurements show mode width of 0.4 µm and effective refractive index of 2.54. Finally, we demonstrate the low loss characteristics of our waveguide by imaging the light scattering using an infrared camera.

Nanoscale mode selector in silicon waveguide for on chip nanofocusing applications.

We demonstrate a nanoscale mode selector supporting the propagation of the first antisymmetric mode of a silicon waveguide. The mode selector is based on embedding a short section of PhC into the waveguide. On the basis of the difference in k-vector distribution between orthogonal waveguide modes, the PhC can be designed to have a band gap for the fundamental mode, while allowing the transmission of the first antisymmetric mode. The device was tested by directly measuring the modal content before and after the PhC section using a near field scanning optical microscope. Extinction ratio was estimated to be approximately 23 dB. Finally, we provide numerical simulations demonstrating strong coupling of the antisymmetric mode to metallic nanotips. On the basis of the results, we believe that the mode selector may become an important building block in the realization of on chip nanofocusing devices.

High resolution direct measurement of temperature distribution in silicon nanophotonics devices.

Following the miniaturization of photonic devices and the increase in data rates, the issues of self heating and heat removal in active nanophotonic devices should be considered and studied in more details. In this paper we use the approach of Scanning Thermal Microscopy (SThM) to obtain an image of the temperature field of a silicon micro ring resonator with sub-micron spatial resolution. The temperature rise in the device is a result of self heating which is caused by free carrier absorption in the doped silicon. The temperature is measured locally and directly using a temperature sensitive AFM probe. We show that this local temperature measurement is feasible in the photonic device despite the perturbation that is introduced by the probe. Using the above method we observed a significant self heating of about 10 degrees within the device.

Integration of silicon plasmonic schottky photodetector for on chip signal tapping at telecom wavelengths

We experimentally demonstrate the use of an on-chip integrated Schottky plasmonic detector for testing, monitoring and tapping signals in plasmonic and photonic devices. Theoretical model and measurement of external and integrated devices will be presented. © OSA 2013.