Switching speed enhancement of the LDMOSFETs using partial-SOI technology

To overcome reduced breakdown voltage and self-heating effects inherent in silicon-on-insulator (SOI) power integrated circuits while still maintaining good isolation between low power CMOS circuits and the high power cells, partial SOI (PSOI) technology has been proposed. PSOI devices make use of both buried oxide and substrate depletion to support the breakdown voltage. 2D analyses and modeling of parasitic capacitances in PSOI structures show that PSOI-lightly doped MOSFETs can increase the switching speed by as much as four times compared to conventional SOI structures, making them very attractive for high switching applications.

Crystal growth of melt-textured Nd-123 under 1% oxygen partial pressure atmosphere

Crystal growth of melt-textured Nd-123 pseudo-crystals was investigated via an isothermal solidification with top-seeding technique under a 1%O2 in N2 atmosphere. Non-steady state solidification was observed at low undercooling, in contrast to an almost linear growth at higher undercooling. Similar to processing in air, the substitution of Nd/Ba was found to decrease from the seed position to the edge of the crystal. In addition, the volume fraction of Nd-422 particles decreased in the solid as solidification proceeded. As a result of these microstructural inhomogeneities, the critical temperature and the critical current density varied within the crystal even for samples processed isothermally, despite the narrow solid solution range of the Nd-123 phase under a reduced pO2 atmosphere.

Low partial pressure chemical vapor deposition of graphene on copper

A systematic study of the Cu-catalyzed chemical vapor deposition of graphene under extremely low partial pressure is carried out. A carbon precursor supply of just P CH4∼ 0.009 mbar during the deposition favors the formation of large-area uniform monolayer graphene verified by Raman spectra. A diluted HNO 3 solution is used to remove Cu before transferring graphene onto SiO 2/Si substrates or carbon grids. The graphene can be made suspended over a ∼12 μm distance, indicating its good mechanical properties. Electron transport measurements show the graphene sheet resistance of ∼0.6 kΩ/□ at zero gate voltage. The mobilities of electrons and holes are ∼1800 cm 2/Vs at 4.2 K and ∼1200 cm 2/Vs at room temperature. © 2011 IEEE.

200-V lateral superjunction LIGBT on partial SOI

This letter presents a novel lateral superjunction lateral insulated-gate bipolar transistor (LIGBT) in partial silicon-on-insulator (SOI) technology in 0.18-μm partial-SOI (PSOI) high-voltage (HV) process. For an n-type superjunction LIGBT, the p-layer in the superjunction drift region not only helps in achieving uniform electric field distribution but also contributes to the on-state current. The superjunction LIGBT successfully achieves a breakdown voltage (BV) of 210 V with an R dson of 765 mΩ ̇ mm 2. It exhibits half the value of specific on-state resistance R dson and three times higher saturation current (I dsat) for the same BV, compared to a comparable lateral superjunction laterally diffused metal-oxide-semiconductor fabricated in the same technology. It also performs well in higher temperature dc operation with 38.8% increase in R dson at 175°C, compared to the room temperature without any degradation in latch-up performance. To realize this device, it only requires one additional mask layer into X-FAB 0.18-μm PSOI HV process. © 2012 IEEE.