A packaging technique for silicon MEMS strain sensors on steel

A packaging technique suited to applying MEMS strain sensors realized on a silicon chip to a steel flat surface is described. The method is based on adhesive bonding of the silicon chip rear surface on steel using two types of glue normally used for standard piezoresistive strain sensors (Mbond200/ 600), using direct wire bonding of the chip to a Printed Circuit Board, also fixed on steel. In order to protect the sensor from the external environment, and to improve the MEMS performance, the silicon chip is encapsulated with a metal cap hermetically sealed-off under vacuum condition with a vacuum adhesive in which the bonding wires are also protected from possible damage. In order to evaluate the mechanical coupling of the silicon chip with the bar and thestress transfer extent to the silicon surface, commercial strain sensors have been applied on the chip glued on a steel bar in alaboratory setup able to generate strain by inflection, yielding a stress transfer around 70% from steel to silicon. © 2008 IEEE.

A 4 GHz non-resonant clock driver with inductor-assisted energy return to power grid

Power consumption of a multi-GHz local clock driver is reduced by returning energy stored in the clock-tree load capacitance back to the on-chip power-distribution grid. We call this type of return energy recycling. To achieve a nearly square clock waveform, the energy is transferred in a non-resonant way using an on-chip inductor in a configuration resembling a full-bridge DC-DC converter. A zero-voltage switching technique is implemented in the clock driver to reduce dynamic power loss associated with the high switching frequencies. A prototype implemented in 90 nm CMOS shows a power savings of 35% at 4 GHz. The area needed for the inductor in this new clock driver is about 6% of a local clock region. © 2006 IEEE.

Predictive control of a Boeing 747 aircraft using an FPGA

New embedded predictive control applications call for more eficient ways of solving quadratic programs (QPs) in order to meet demanding real-time, power and cost requirements. A single precision QP-on-a-chip controller is proposed, implemented in afield-programmable gate array (FPGA) with an iterative linear solver at its core. A novel offline scaling procedure is introduced to aid the convergence of the reduced precision solver. The feasibility of the proposed approach is demonstrated with a real-time hardware-in-the-loop (HIL) experimental setup where an ML605 FPGA board controls a nonlinear model of a Boeing 747 aircraft running on a desktop PC through an Ethernet link. Simulations show that the quality of the closed-loop control and accuracy of individual solutions is competitive with a conventional double precision controller solving linear systems using a Riccati recursion. © 2012 IFAC.

Verification of periodically controlled hybrid systems: Application to an autonomous vehicle

This article introduces Periodically Controlled Hybrid Automata (PCHA) for modular specification of embedded control systems. In a PCHA, control actions that change the control input to the plant occur roughly periodically, while other actions that update the state of the controller may occur in the interim. Such actions could model, for example, sensor updates and information received from higher-level planning modules that change the set point of the controller. Based on periodicity and subtangential conditions, a new sufficient condition for verifying invariant properties of PCHAs is presented. For PCHAs with polynomial continuous vector fields, it is possible to check these conditions automatically using, for example, quantifier elimination or sum of squares decomposition. We examine the feasibility of this automatic approach on a small example. The proposed technique is also used to manually verify safety and progress properties of a fairly complex planner-controller subsystem of an autonomous ground vehicle. Geometric properties of planner-generated paths are derived which guarantee that such paths can be safely followed by the controller. © 2012 ACM.

Characterization and fabrication of zinc oxide nanowire devices

In this paper, we demonstrate an approach for the local synthesis of ZnO nanowires (ZnO NWs) and the potential for such structures to be incorporated into device applications. Three network ZnO NW devices are fabricated on a chip by using a bottom-up synthesis approach. Microheaters (defined by standard semiconductor processing) are used to synthesize the ZnO NWs under a zinc nitrate (Zn(NO3)2·6H2O) and hexamethylenetetramine (HMTA, (CH2)6·N4) solution. By controlling synthesis parameters, varying densities of networked ZnO NWs are locally synthesized on the chip. The fabricated networked ZnO NW devices are then characterized using UV excitation and cyclic voltammetry (CV) experiments to measure their photoresponse and electrochemical properties. The experimental results show that the techniques and material systems presented here have the potential to address interesting device applications using fabrication methods that are fully compatible with standard semiconductor processing. © 2013 IEEE.

Predictive control using an FPGA with application to aircraft control

Alternative and more efficient computational methods can extend the applicability of model predictive control (MPC) to systems with tight real-time requirements. This paper presents a system-on-a-chip MPC system, implemented on a field-programmable gate array (FPGA), consisting of a sparse structure-exploiting primal dual interior point (PDIP) quadratic program (QP) solver for MPC reference tracking and a fast gradient QP solver for steady-state target calculation. A parallel reduced precision iterative solver is used to accelerate the solution of the set of linear equations forming the computational bottleneck of the PDIP algorithm. A numerical study of the effect of reducing the number of iterations highlights the effectiveness of the approach. The system is demonstrated with an FPGA-in-the-loop testbench controlling a nonlinear simulation of a large airliner. This paper considers many more manipulated inputs than any previous FPGA-based MPC implementation to date, yet the implementation comfortably fits into a midrange FPGA, and the controller compares well in terms of solution quality and latency to state-of-the-art QP solvers running on a standard PC. © 1993-2012 IEEE.