Standard cell automated layout for a CMOS 50 MHz 8 × 8 bit pipelined parallel dadda multiplier

An 8 × 8 pipelined parallel multiplier which uses the Dadda scheme is presented. The multiplier has been implemented in a 3-μm n-well CMOS process with two layers of metal using a standard cell automatic placement and routing program. The design uses a form of pipelined carry look-ahead adder in the final stage of summation, thus providing a significant contribution to the high performance of the multiplier. The design is expected to operate at a clock frequency of at least 50 MHz and has a flush time of seven clock cycles. The design illustrates a possible method of implementing an irregular architecture in VLSI using multiple levels of low-resistance, low-capacitance interconnect and automated layout techniques.

SUB-BAND CODING TECHNIQUES FOR ROBUST 4. 8 TO 8 kb/s SPEECH CODERS.

This paper describes a speech coding technique that has been developed in order to provide a method of digitising speech at bit rates in the range 4. 8 to 8 kb/s, that is insensitive to the effects of acoustic background noise and bit errors on the digital link. The main aim has been to develop a coding scheme which provides speech quality and robustness against noise and errors that is similar to a 16000 b/s continuously variable slope delta (CVSD) coder, but which operates at half its data rate or less. A desirable aim was to keep the complexity of the coding scheme within the scope of what could reasonably be handled by current signal processing chips or by a single custom integrated circuit. Applications areas include mobile radio and small Satcomms terminals.

Single domain YBCO/Ag bulk superconductors fabricated by seeded infiltration and growth

We have applied the seeded infiltration and growth (IG) technique to the processing of samples containing Ag in an attempt to fabricate Ag-doped Y-Ba-Cu-O (YBCO) bulk superconductors with enhanced mechanical properties. The IG technique has been used successfully to grow bulk Ag-doped YBCO superconductors of up to 25 mm in diameter in the form of single grains. The distribution of Ag in the parent Y-123 matrix fabricated by the IG technique is observed to be at least as uniform as that in samples grown by conventional top seeded melt growth (TSMG). Fine Y-211 particles were observed to be embedded within the Y-123 matrix for the IG processed samples, leading to a high critical current density, Jc, of over 70 kA/cm2 at 77.3 K in self-field. The distribution of Y-211 in the IG sample microstructure, however, is inhomogeneous, which leads to a variation in the spatial distribution of Jc throughout the bulk matrix. A maximum-trapped field of around 0.43 T at 1.2 mm above the sample surface (i.e. including 0.7 mm for the sensor mould thickness) is observed at liquid nitrogen temperature, despite the relatively small grain size of the sample (20 mm diameter × 7 mm thickness). © 2008 IOP Publishing Ltd.