Low on-resistance SOI dual-trench-gate MOSFET

A low specific on-resistance (R-{{\rm on}, {\rm sp}}) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation. The SOI MOSFET features double trenches and dual gates (DTDG SOI): an oxide trench in the drift region, a buried gate inset in the oxide trench, and another trench gate (TG) extended to a buried oxide layer. First, the dual gates form dual conduction channels, and the extended gate widens the vertical conduction area; both of which sharply reduce R-{{\rm on}, {\rm sp}}. Second, the oxide trench folds the drift region in the vertical direction, resulting in a reduced device pitch and R-{{\rm on}, {\rm sp}}. Third, the oxide trench causes multidirectional depletion. This not only enhances the reduced surface field effect and thus reshapes the electric field distribution but also increases the drift doping concentration, leading to a reduced R-{{\rm on}, {\rm sp}} and an improved breakdown voltage (BV). Compared with a conventional SOI lateral Double-diffused metal oxide semiconductor (LDMOS), the DTDG MOSFET increases BV from 39 to 92 V at the same cell pitch or decreases R-{{\rm on}, { \rm sp}} by 77% at the same BV by simulation. Finally, the TG extended synchronously acts as an isolation trench between the high/low-voltage regions in a high-voltage integrated circuit, saving the chip area and simplifying the isolation process. © 2006 IEEE.

Zinc oxide nanowire based hydrogen sensor on SOI CMOS platform

Here we report on the successful low-temperature growth of zinc oxide nanowires (ZnONWs) on silicon-on-insulator (SOI) CMOS micro-hotplates and their response, at different operating temperatures, to hydrogen in air. The SOI micro-hotplates were fabricated in a commercial CMOS foundry followed by a deep reactive ion etch (DRIE) in a MEMS foundry to form ultra-low power membranes. The micro-hotplates comprise p+ silicon micro-heaters and interdigitated metal electrodes (measuring the change in resistance of the gas sensitive nanomaterial). The ZnONWs were grown as a post-CMOS process onto the hotplates using a CMOS friendly hydrothermal method. The ZnONWs showed a good response to 500 to 5000 ppm of hydrogen in air. We believe that the integration of ZnONWs with a MEMS platform results in a low power, low cost, hydrogen sensor that would be suitable for handheld battery-operated gas sensors. © 2011 Published by Elsevier Ltd.

200-V lateral superjunction LIGBT on partial SOI

This letter presents a novel lateral superjunction lateral insulated-gate bipolar transistor (LIGBT) in partial silicon-on-insulator (SOI) technology in 0.18-μm partial-SOI (PSOI) high-voltage (HV) process. For an n-type superjunction LIGBT, the p-layer in the superjunction drift region not only helps in achieving uniform electric field distribution but also contributes to the on-state current. The superjunction LIGBT successfully achieves a breakdown voltage (BV) of 210 V with an R dson of 765 mΩ ̇ mm 2. It exhibits half the value of specific on-state resistance R dson and three times higher saturation current (I dsat) for the same BV, compared to a comparable lateral superjunction laterally diffused metal-oxide-semiconductor fabricated in the same technology. It also performs well in higher temperature dc operation with 38.8% increase in R dson at 175°C, compared to the room temperature without any degradation in latch-up performance. To realize this device, it only requires one additional mask layer into X-FAB 0.18-μm PSOI HV process. © 2012 IEEE.

200V superjunction lateral IGBT fabricated on partial SOI

A 200V lateral insulated gate bipolar transistor (LIGBT) was successfully developed using lateral superjunction (SJ) in 0.18μm partial silicon on insulator (SOI) HV process. The results presented are based on extensive experimental measurements and numerical simulations. For an n-type lateral SJ LIGBT, the p layer in the SJ drift region helps in achieving uniform electric field distribution. Furthermore, the p-pillar contributes to the on-state current. Furthermore, the p-pillar contributes to sweep out holes during the turn-off process, thus leading to faster removal of plasma. To realize this device, one additional mask layer is required in the X-FAB 0.18μm partial SOI HV process. © 2013 IEEE.

Partial soi power LDMOS with a variable low-kappa; Dielectric buried layer and a buried P layer

A power LDMOS on partial silicon on insulator (PSOI) with a variable low-κ dielectric (VLKD) buried layer and a buried p (BP) layer is proposed (VLKD BPSOI). At a low κ value, the electric field strength in the buried dielectric (EI) is enhanced, and a Si window makes the substrate share the vertical voltage drop, leading to a high vertical breakdown voltage (BV). Moreover, three interface field peaks are introduced by the BP, the Si window, and the VLKD, which modulate the fields in the SOI layer, the VLKD layer, and the substrate; consequently, a high BV is obtained. Furthermore, the BP reduces the specific on-resistance (Ron), and the Si window alleviates the self-heating effect (SHE). The BV for VLKD BPSOI is enhanced by 34.5%, and Ron is decreased by 26.6%, compared with those for the conventional PSOI, and VLKD BPSOI also maintains a low SHE. © 2006 IEEE.

A bulk acoustic mode single-crystal silicon microresonator with a high-quality factor

This paper details a bulk acoustic mode resonator fabricated in single-crystal silicon with a quality factor of 15 000 in air, and over a million below 10 mTorr at a resonant frequency of 2.18 MHz. The resonator is a square plate that is excited in the square-extensional mode and has been fabricated in a commercial foundry silicon-on-insulator (SOI) MEMS process through MEMSCAP. This paper also presents a simple method of extracting resonator parameters from raw measurements heavily buried in electrical feedthrough. Its accuracy has been demonstrated through a comparison between extracted motional resistance values measured at different voltage biases and those predicted from an analytical model. Finally, a method of substantially cancelling electrical feedthrough through system-level electronic implementation is also introduced. © 2008 IOP Publishing Ltd.

Study of lateral mode SOI-MEMS resonators for reduced anchor loss

MEMS resonators fabricated in silicon-on-insulator (SOI) technology must be clamped to the substrate via anchoring stems connected either from within the resonator or through the sides, with the side-clamped solution often employed due to manufacturing constraints. This paper examines the effect of two types of commonly used side-clamped, anchoring-stem geometries on the quality factor of three different laterally-driven resonator topologies. This study employs an analytical framework which considers the relative distribution of strain energies between the resonating body and clamping stems. The ratios of the strain energies are computed using ANSYS FEA and used to provide an indicator of the expected anchor-limited quality factors. Three MEMS resonator topologies have been fabricated and characterized in moderate vacuum. The associated measured quality factors are compared against the computed strain energy ratios, and the trends are shown to agree well with the experimental data. © 2011 IOP Publishing Ltd.

Switching speed enhancement of the LDMOSFETs using partial-SOI technology

To overcome reduced breakdown voltage and self-heating effects inherent in silicon-on-insulator (SOI) power integrated circuits while still maintaining good isolation between low power CMOS circuits and the high power cells, partial SOI (PSOI) technology has been proposed. PSOI devices make use of both buried oxide and substrate depletion to support the breakdown voltage. 2D analyses and modeling of parasitic capacitances in PSOI structures show that PSOI-lightly doped MOSFETs can increase the switching speed by as much as four times compared to conventional SOI structures, making them very attractive for high switching applications.

SOI diode temperature sensor operated at ultra high temperatures-a critical analysis

This paper investigates the performance of diode temperature sensors when operated at ultra high temperatures (above 250°C). A low leakage Silicon On Insulator (SOI) diode was designed and fabricated in a 1 μm CMOS process and suspended within a dielectric membrane for efficient thermal insulation. The diode can be used for accurate temperature monitoring in a variety of sensors such as microcalorimeters, IR detectors, or thermal flow sensors. A CMOS compatible micro-heater was integrated with the diode for local heating. It was found that the diode forward voltage exhibited a linear dependence on temperature as long as the reverse saturation current remained below the forward driving current. We have proven experimentally that the maximum temperature can be as high as 550°C. Long term continuous operation at high temperatures (400°C) showed good stability of the voltage drop. Furthermore, we carried out a detailed theoretical analysis to determine the maximum operating temperature and exlain the presence of nonlinearity factors at ultra high temperatures. © 2008 IEEE.

Laminar to turbulent flow transition measurements using an array of SOI-CMOS MEMS wall shear stress sensors

The successful utilization of an array of silicon on insulator complementary metal oxide semiconductor (SOICMOS) micro thermal shear stress sensors for flow measurements at macro-scale is demonstrated. The sensors use CMOS aluminum metallization as the sensing material and are embedded in low thermal conductivity silicon oxide membranes. They have been fabricated using a commercial 1 μm SOI-CMOS process and a post-CMOS DRIE back etch. The sensors with two different sizes were evaluated. The small sensors (18.5 ×18.5 μm2 sensing area on 266 × 266 μm2 oxide membrane) have an ultra low power (100 °C temperature rise at 6mW) and a small time constant of only 5.46 μs which corresponds to a cut-off frequency of 122 kHz. The large sensors (130 × 130 μm2 sensing area on 500 × 500 μm2 membrane) have a time constant of 9.82 μs (cut-off frequency of 67.9 kHz). The sensors' performance has proven to be robust under transonic and supersonic flow conditions. Also, they have successfully identified laminar, separated, transitional and turbulent boundary layers in a low speed flow. © 2008 IEEE.

SOI membrane-based pressure sensor in stress sensitive differential amplifier configuration

This paper introduces a pressure sensing structure configured as a stress sensitive differential amplifier (SSDA), built on a Silicon-on-Insulator (SOI) membrane. Theoretical calculation show the significant increase in sensitivity which is expected from the pressure sensors in SSDA configuration compared to the traditional Wheatstone bridge circuit. Preliminary experimental measurements, performed on individual transistors placed on the membrane, exhibit state-the-art sensitivity values (1.45mV/mbar). © 2012 IEEE.