Performance of CMOS Devices in Silicon-on-Sapphire Films After Solid-Phase Epitaxial Growth With Rapid Electron-Beam Heating

The crystal quality of 0.3-μm-thick as-grown epitaxial silicon-on-sapphire (SOS) was improved using solid-phase epitaxy (SPE) by implantation with silicon to 1015 ions/cm2 at 175 keV and rapid annealing using electron-beam heating, n-channel and p-channel transistormobilities increased by 31 and 19 percent, respectively, and a reduction in ring-oscillator stage delay confirmed that crystal defects near the upper silicon surface had been removed. Leakage in n-channel transistors was not significantly affected by the regrowth process but for p-channel transistors back-channel leakage was considerably greater than for the control devices. This is attributed to aluminum released by damage to the sapphire during silicon implantation. © 1985 IEEE

REGROWTH RATES OF AMORPHOUS LAYERS IN SILICON-ON-SAPPHIRE FILMS.

The rate and direction of regrowth of amorphous layers, created by self-implantation, in silicon-on-sapphire (SOS) have been studied using time resolved reflectivity (TRR) experiments performed simultaneously at two wavelengths. Regrowth of an amorphous layer towards the surface was observed in specimens implanted with 3 multiplied by (times) 10**1**5Si** plus /cm**2 at 50keV and regrowth of a buried amorphous layer, from a surface seed towards the sapphire, was observed in specimens implanted with 1 multiplied by (times) 10**1**5Si** plus /cm**2 at 175keV. Rapid isothermal heating to regrow the layers was performed in an electron beam annealing system. The combination of 514. 5nm and 632. 8nm wavelengths was found to be particularly useful for TRR studies since the high absorption in amorphous silicon, at the shorter wavelength, means that the TRR trace is not complicated by reflection from the silicon-sapphire interface until regrowth is nearly complete.

Smart chemical sensor application of ZnO nanowires grown on CMOS compatible SOI microheater platform

Smart chemical sensor based on CMOS(complementary metal-oxide- semiconductor) compatible SOI(silicon on insulator) microheater platform was realized by facilitating ZnO nanowires growth on the small membrane at the relatively low temperature. Our SOI microheater platform can be operated at the very low power consumption with novel metal oxide sensing materials, like ZnO or SnO2 nanostructured materials which demand relatively high sensing temperature. In addition, our sol-gel growth method of ZnO nanowires on the SOI membrane was found to be very effective compared with ink-jetting or CVD growth techniques. These combined techniques give us the possibility of smart chemical sensor technology easily merged into the conventional semiconductor IC application. The physical properties of ZnO nanowire network grown by the solution-based method and its chemical sensing property also were reported in this paper.

Low on-resistance SOI dual-trench-gate MOSFET

A low specific on-resistance (R-{{\rm on}, {\rm sp}}) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation. The SOI MOSFET features double trenches and dual gates (DTDG SOI): an oxide trench in the drift region, a buried gate inset in the oxide trench, and another trench gate (TG) extended to a buried oxide layer. First, the dual gates form dual conduction channels, and the extended gate widens the vertical conduction area; both of which sharply reduce R-{{\rm on}, {\rm sp}}. Second, the oxide trench folds the drift region in the vertical direction, resulting in a reduced device pitch and R-{{\rm on}, {\rm sp}}. Third, the oxide trench causes multidirectional depletion. This not only enhances the reduced surface field effect and thus reshapes the electric field distribution but also increases the drift doping concentration, leading to a reduced R-{{\rm on}, {\rm sp}} and an improved breakdown voltage (BV). Compared with a conventional SOI lateral Double-diffused metal oxide semiconductor (LDMOS), the DTDG MOSFET increases BV from 39 to 92 V at the same cell pitch or decreases R-{{\rm on}, { \rm sp}} by 77% at the same BV by simulation. Finally, the TG extended synchronously acts as an isolation trench between the high/low-voltage regions in a high-voltage integrated circuit, saving the chip area and simplifying the isolation process. © 2006 IEEE.

Zinc oxide nanowire based hydrogen sensor on SOI CMOS platform

Here we report on the successful low-temperature growth of zinc oxide nanowires (ZnONWs) on silicon-on-insulator (SOI) CMOS micro-hotplates and their response, at different operating temperatures, to hydrogen in air. The SOI micro-hotplates were fabricated in a commercial CMOS foundry followed by a deep reactive ion etch (DRIE) in a MEMS foundry to form ultra-low power membranes. The micro-hotplates comprise p+ silicon micro-heaters and interdigitated metal electrodes (measuring the change in resistance of the gas sensitive nanomaterial). The ZnONWs were grown as a post-CMOS process onto the hotplates using a CMOS friendly hydrothermal method. The ZnONWs showed a good response to 500 to 5000 ppm of hydrogen in air. We believe that the integration of ZnONWs with a MEMS platform results in a low power, low cost, hydrogen sensor that would be suitable for handheld battery-operated gas sensors. © 2011 Published by Elsevier Ltd.

200-V lateral superjunction LIGBT on partial SOI

This letter presents a novel lateral superjunction lateral insulated-gate bipolar transistor (LIGBT) in partial silicon-on-insulator (SOI) technology in 0.18-μm partial-SOI (PSOI) high-voltage (HV) process. For an n-type superjunction LIGBT, the p-layer in the superjunction drift region not only helps in achieving uniform electric field distribution but also contributes to the on-state current. The superjunction LIGBT successfully achieves a breakdown voltage (BV) of 210 V with an R dson of 765 mΩ ̇ mm 2. It exhibits half the value of specific on-state resistance R dson and three times higher saturation current (I dsat) for the same BV, compared to a comparable lateral superjunction laterally diffused metal-oxide-semiconductor fabricated in the same technology. It also performs well in higher temperature dc operation with 38.8% increase in R dson at 175°C, compared to the room temperature without any degradation in latch-up performance. To realize this device, it only requires one additional mask layer into X-FAB 0.18-μm PSOI HV process. © 2012 IEEE.

Room-temperature emission at telecom wavelengths from silicon photonic crystal nanocavities

Strongly enhanced light emission at wavelengths between 1.3 and 1.6 μm is reported at room temperature in silicon photonic crystal (PhC) nanocavities with optimized out-coupling efficiency. Sharp peaks corresponding to the resonant modes of PhC nanocavities dominate the broad sub-bandgap emission from optically active defects in the crystalline Si membrane. We measure a 300-fold enhancement of the emission from the PhC nanocavity due to a combination of far-field enhancement and the Purcell effect. The cavity enhanced emission has a very weak temperature dependence, namely less than a factor of 2 reduction between 10 K and room temperature, which makes this approach suitable for the realization of efficient light sources as well as providing a quick and easy tool for the broadband optical characterization of silicon-on-insulator nanostructures. © 2011 American Institute of Physics.

Locally oxidized silicon surface-plasmon Schottky detector for telecom regime.

We experimentally demonstrate an on-chip nanoscale silicon surface-plasmon Schottky photodetector based on internal photoemission process and operating at telecom wavelengths. The device is fabricated using a self-aligned approach of local-oxidation of silicon (LOCOS) on silicon on insulator substrate, which provides compatibility with standard complementary metal-oxide semiconductor technology and enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. Additionally, LOCOS technique allows avoiding lateral misalignment between the silicon surface and the metal layer to form a nanoscale Schottky contact. The fabricated devices showed enhanced detection capability for shorter wavelengths that is attributed to increased probability of the internal photoemission process. We found the responsivity of the nanodetector to be 0.25 and 13.3 mA/W for incident optical wavelengths of 1.55 and 1.31 μm, respectively. The presented device can be integrated with other nanophotonic and nanoplasmonic structures for the realization of monolithic opto-electronic circuitry on-chip.

Locally oxidized silicon surface-plasmon Schottky detector for telecom regime

We experimentally demonstrate an on-chip nanoscale silicon surface-plasmon Schottky photodetector based on internal photoemission process and operating at telecom wavelengths. The device is fabricated using a self-aligned approach of local-oxidation of silicon (LOCOS) on silicon on insulator substrate, which provides compatibility with standard complementary metal-oxide semiconductor technology and enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. Additionally, LOCOS technique allows avoiding lateral misalignment between the silicon surface and the metal layer to form a nanoscale Schottky contact. The fabricated devices showed enhanced detection capability for shorter wavelengths that is attributed to increased probability of the internal photoemission process. We found the responsivity of the nanodetector to be 0.25 and 13.3 mA/W for incident optical wavelengths of 1.55 and 1.31 μm, respectively. The presented device can be integrated with other nanophotonic and nanoplasmonic structures for the realization of monolithic opto-electronic circuitry on-chip. © 2011 American Chemical Society.

200V superjunction lateral IGBT fabricated on partial SOI

A 200V lateral insulated gate bipolar transistor (LIGBT) was successfully developed using lateral superjunction (SJ) in 0.18μm partial silicon on insulator (SOI) HV process. The results presented are based on extensive experimental measurements and numerical simulations. For an n-type lateral SJ LIGBT, the p layer in the SJ drift region helps in achieving uniform electric field distribution. Furthermore, the p-pillar contributes to the on-state current. Furthermore, the p-pillar contributes to sweep out holes during the turn-off process, thus leading to faster removal of plasma. To realize this device, one additional mask layer is required in the X-FAB 0.18μm partial SOI HV process. © 2013 IEEE.

Partial soi power LDMOS with a variable low-kappa; Dielectric buried layer and a buried P layer

A power LDMOS on partial silicon on insulator (PSOI) with a variable low-κ dielectric (VLKD) buried layer and a buried p (BP) layer is proposed (VLKD BPSOI). At a low κ value, the electric field strength in the buried dielectric (EI) is enhanced, and a Si window makes the substrate share the vertical voltage drop, leading to a high vertical breakdown voltage (BV). Moreover, three interface field peaks are introduced by the BP, the Si window, and the VLKD, which modulate the fields in the SOI layer, the VLKD layer, and the substrate; consequently, a high BV is obtained. Furthermore, the BP reduces the specific on-resistance (Ron), and the Si window alleviates the self-heating effect (SHE). The BV for VLKD BPSOI is enhanced by 34.5%, and Ron is decreased by 26.6%, compared with those for the conventional PSOI, and VLKD BPSOI also maintains a low SHE. © 2006 IEEE.

Square wine glass mode resonator with quality factor of 4 million

We report on the experimental characterization of a single crystal silicon square-plate microresonator. The resonator is excited in the square wine glass (SWG) mode at a mechanical resonance frequency of 2.065 MHz. The resonator displays quality factor of 9660 in air and an ultra-high quality factor of Q = 4.05 × 106 in 12 mtorr vacuum. The SWG mode may be described as a square plate that contracts along one axis in the fabrication plane, while simultaneously extending along an orthogonal axis in the same plane. The resonant structure is addressed in a 2-terminal configuration by utilizing equal and opposite drive polarities on surrounding capacitor electrodes, thereby decreasing the motional resistance of the resonator. The resonant micromechanical device has been fabricated in a commercial silicon-on-insulator process through the MEMSCAP foundry utilising a minimum electrostatic gap of 2 μm. © 2008 IEEE.

Study of lateral mode SOI-MEMS resonators for reduced anchor loss

MEMS resonators fabricated in silicon-on-insulator (SOI) technology must be clamped to the substrate via anchoring stems connected either from within the resonator or through the sides, with the side-clamped solution often employed due to manufacturing constraints. This paper examines the effect of two types of commonly used side-clamped, anchoring-stem geometries on the quality factor of three different laterally-driven resonator topologies. This study employs an analytical framework which considers the relative distribution of strain energies between the resonating body and clamping stems. The ratios of the strain energies are computed using ANSYS FEA and used to provide an indicator of the expected anchor-limited quality factors. Three MEMS resonator topologies have been fabricated and characterized in moderate vacuum. The associated measured quality factors are compared against the computed strain energy ratios, and the trends are shown to agree well with the experimental data. © 2011 IOP Publishing Ltd.