352 resultados para Quantum Gate


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We describe the fabrication of self-aligned split gate electrodes on suspended multiwalled carbon nanotube structures. A suspended multiwalled carbon nanotube structure was used as an evaporation mask for the deposition of metal electrodes resulting in the formation of discontinuous wire deposition. The metal deposits on the nanotubes are removed with lift-off due to the poor adhesion of metal to the nanotube surface. Using Al sacrificial layers, it was possible to fabricate self-aligned contact electrodes and control electrodes nanometers from the suspended carbon nanotubes with a single lithography step. It was also shown that the fabrication technique may also be used to form nano-gaped contact electrodes. The technique should prove useful for the fabrication of nano-electromechanical systems.

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We describe the fabrication of self-aligned split gate electrodes on suspended multiwalled carbon nanotube structures. A suspended multiwalled carbon nanotube structure was used as an evaporation mask for the deposition of metal electrodes resulting in the formation of discontinuous wire deposition. The metal deposits on the nanotubes are removed with lift-off due to the poor adhesion of metal to the nanotube surface. Using Al sacrificial layers, it was possible to fabricate self-aligned contact electrodes and control electrodes nanometers from the suspended carbon nanotubes with a single lithography step. It was also shown that the fabrication technique may also be used to form nano-gaped contact electrodes. The technique should prove useful for the fabrication of nano-electromechanical systems. © 2003 Materials Research Society.

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The subthreshold slope, transconductance, threshold voltage, and hysteresis of a carbon nanotube field-effect transistor (CNT FET) were examined as its configuration was changed from bottom-gate exposed channel, bottom-gate covered channel to top-gate FET. An individual single wall CNT was grown by chemical vapor deposition and its gate configuration was changed while determining its transistor characteristics to ensure that the measurements were not a function of different chirality or diameter CNTs. The bottom-gate exposed CNT FET utilized 900 nm SiO2 as the gate insulator. This CNT FET was then covered with TiO2 to form the bottom-gate covered channel CNT FET. Finally, the top-gate CNT FET was fabricated and the device utilized TiO 2 (K ∼ 80, equivalent oxide thickness=0.25 nm) as the gate insulator. Of the three configurations investigated, the top-gate device exhibited best subthreshold slope (67-70 mV/dec), highest transconductance (1.3 μS), and negligible hysteresis in terms of threshold voltage shift. © 2006 American Institute of Physics.