Standard cell automated layout for a CMOS 50 MHz 8 × 8 bit pipelined parallel dadda multiplier

An 8 × 8 pipelined parallel multiplier which uses the Dadda scheme is presented. The multiplier has been implemented in a 3-μm n-well CMOS process with two layers of metal using a standard cell automatic placement and routing program. The design uses a form of pipelined carry look-ahead adder in the final stage of summation, thus providing a significant contribution to the high performance of the multiplier. The design is expected to operate at a clock frequency of at least 50 MHz and has a flush time of seven clock cycles. The design illustrates a possible method of implementing an irregular architecture in VLSI using multiple levels of low-resistance, low-capacitance interconnect and automated layout techniques.

Experimental demonstration of femtosecond switching of a fully packaged all-optical switch

We experimentally demonstrate femtosecond switching of a fully packaged hybrid-integrated Mach-Zehnder switch. A record switching window of 620fs at fult-width-half-maximum is achieved. © 2004 Optical Society of America.

Biomimetic bone-like composites fabricated through an automated alternate soaking process.

Hydroxyapatite-gelatin composites have been proposed as suitable scaffolds for bone and dentin tissue regeneration. There is considerable interest in producing these scaffolds using biomimetic methods due to their low energy costs and potential to create composites similar to the tissues they are intended to replace. Here an existing process used to coat a surface with hydroxyapatite under near physiological conditions, the alternate soaking process, is modified and automated using an inexpensive "off the shelf" robotics kit. The process is initially used to precipitate calcium phosphate coatings. Then, in contrast to previous utilizations of the alternate soaking process, gelatin was added directly to the solutions in order to co-precipitate hydroxyapatite-gelatin composites. Samples were investigated by Fourier transform infrared spectroscopy, scanning electron microscopy, energy dispersive X-ray spectroscopy and nanoindentation. Calcium phosphate coatings formed by the alternate soaking process exhibited different calcium to phosphate ratios, with correspondingly distinct structural morphologies. The coatings demonstrated an interconnected structure with measurable mechanical properties, even though they were 95% porous. In contrast, hydroxyapatite-gelatin composite coatings over 2mm thick could be formed with little visible porosity. The hydroxyapatite-gelatin composites demonstrate a composition and mechanical properties similar to those of cortical bone.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.