Programmable ZnO nanowire transistors using switchable polarization of ferroelectric liquid crystal

We demonstrate modulations of electrical conductance and hysteresis behavior in ZnO nanowire transistors via electrically polarized switching of ferroelectric liquid crystal (FLC). After coating a nanowire channel in the transistors with FLCs, we observed large increases in channel conductance and hysteresis width, and a strong dependence of hysteresis loops on the polarization states associated with the orientation of electric dipole moments along the direction of the gate electric field. Furthermore, the reversible switching and retention characteristics provide the feasibility of creating a hybrid system with switch and memory functions. © 2013 American Institute of Physics.

Novel field emission from graphene sheets supported by CNTs arrays

A good quality graphene is transferred onto honeycomb-like CNTs arrays with inner supporting CNTs. The efficient field emission is demonstrated due to a high aspect ratio protrusions and graphene crack edges. A high efficient current density about 1.2 mA/cm2 at threshold electric field of 7.8 V/μm with a turn-on electric field of 1.8 V/μm at the current density of 10 μA/cm2 is observed due to high localized electric field. Stable field emission is tested in a vacuum chamber. The results are of significance to the development of Graphene based field emitters. © 2013 IEEE.

A comparative study of plasma-enhanced chemical vapor gate dielectrics for solution-processed polymer thin-film transistor circuit integration

This paper considers plasma-enhanced chemical vapor deposited (PECVD) silicon nitride (SiNx) and silicon oxide (SiOx) as gate dielectrics for organic thin-film transistors (OTFTs), with solution-processed poly[5, 5′ -bis(3-dodecyl-2-thienyl)-2, 2′ -bithiophene] (PQT-12) as the active semiconductor layer. We examine transistors with SiNx films of varying composition deposited at 300 °C as well as 150 °C for plastic compatibility. The transistors show over 100% (two times) improvement in field-effect mobility as the silicon content in SiNx increases, with mobility (μFE) up to 0.14 cm2 /V s and on/off current ratio (ION / IOFF) of 108. With PECVD SiOx gate dielectric, preliminary devices exhibit a μFE of 0.4 cm2 /V s and ION / IOFF of 108. PQT-12 OTFTs with PECVD SiNx and SiOx gate dielectrics on flexible plastic substrates are also presented. These results demonstrate the viability of using PECVD SiN x and SiOx as gate dielectrics for OTFT circuit integration, where the low temperature and large area deposition capabilities of PECVD films are highly amenable to integration of OTFT circuits targeted for flexible and lightweight applications. © 2008 American Institute of Physics.

Measurement and simulation of surface roughness noise using phased microphone arrays

A turbulent boundary-layer flow over a rough wall generates a dipole sound field as the near-field hydrodynamic disturbances in the turbulent boundary-layer scatter into radiated sound at small surface irregularities. In this paper, phased microphone arrays are applied to the measurement and simulation of surface roughness noise. The radiated sound from two rough plates and one smooth plate in an open jet is measured at three streamwise locations, and the beamforming source maps demonstrate the dipole directivity. Higher source strengths can be observed on the rough plates which also enhance the trailing-edge noise. A prediction scheme in previous theoretical work is used to describe the strength of a distribution of incoherent dipoles and to simulate the sound detected by the microphone array. Source maps of measurement and simulation exhibit satisfactory similarities in both source pattern and source strength, which confirms the dipole nature and the predicted magnitude of roughness noise. However, the simulations underestimate the streamwise gradient of the source strengths and overestimate the source strengths at the highest frequency. © 2008 Elsevier Ltd. All rights reserved.

Plasma enhanced chemical vapour deposited carbon nanotubes for field emission applications

Plasma Enhanced Chemical Vapour Deposition is an extremely versatile technique for directly growing multiwalled carbon nanotubes onto various substrates. We will demonstrate the deposition of vertically aligned nanotube arrays, sparsely or densely populated nanotube forests, and precisely patterned arrays of nanotubes. The high-aspect ratio nanotubes (∼50 nm in diameter and 5 microns long) produced are metallic in nature and direct contact electrical measurements reveal that each nanotube has a current carrying capacity of 107-108 A/cm2, making them excellent candidates as field emission sources. We examined the field emission characteristics of dense nanotube forests as well as sparse nanotube forests and found that the sparse forests had significantly lower turn-on fields and higher emission currents. This is due to a reduction in the field enhancement of the nanotubes due to electric field shielding from adjacent nanotubes in the dense nanotube arrays. We thus fabricated a uniform array of single nanotubes to attempt to overcome these issues and will present the field emission characteristics of this.

Carbon nanotube Schottky diode and directionally dependent field-effect transistor using asymmetrical contacts

We demonstrate the fabrication and operation of a carbon nanotube (CNT) based Schottky diode by using a Pd contact (high-work-function metal) and an Al contact (low-work-function metal) at the two ends of a single-wall CNT. We show that it is possible to tune the rectification current-voltage (I-V) characteristics of the CNT through the use of a back gate. In contrast to standard back gate field-effect transistors (FET) using same-metal source drain contacts, the asymmetrically contacted CNT operates as a directionally dependent CNT FET when gated. While measuring at source-drain reverse bias, the device displays semiconducting characteristics whereas at forward bias, the device is nonsemiconducting. © 2005 American Institute of Physics.

Electron emission from arrays of carbon nanotubes/fibres

The overall aim of this work is to produce arrays of field emitting microguns, based on carbon nanotubes, which can be utilised in the manufacture of large area field emitting displays, parallel e-beam lithography systems and electron sources for high frequency amplifiers. This paper will describe the work carried out to produce patterned arrays of aligned multiwall carbon nanotubes (MWCNTs) using a dc plasma technique and a Ni catalyst. We will discuss how the density of the carbon nanotube/fibres can be varied by reducing the deposition yield through nickel interaction with a diffusion layer or by direct lithographic patterning of the Ni catalyst to precisely define the position of each nanotube/fibre. Details of the field emission behaviour of the different arrays of MWCNTS will also be presented. © 2002 Published by Elsevier Science B.V.

Direct growth of horizontally aligned carbon nanotubes between electrodes and its application to field-effect transistors

This paper presents direct growth of horizontally aligned carbon nanotubes (CNTs) between two predefined various inter-spacing up to tens of microns of electrodes (pads) and its use as CNT field-effect transistors (CNT-FETs). The catalytic metals were prepared, consisting of iron (Fe), aluminum (Al) and platinum (Pt) triple layers, on the thermal silicon oxide substrate (Pt/Al/Fe/SiO2). Scanning electron microscopy measurements of CNT-FETs from the as-grown samples showed that over 80% of the nanotubes are grown across the catalytic electrodes. Moreover, the number of CNTs across the catalytic electrodes is roughly controllable by adjusting the growth condition. The Al, as the upper layer on Fe electrode, not only plays a role as a barrier to prevent vertical growth but also serves as a porous medium that helps in forming smaller nano-sized Fe particles which would be necessary for lateral growth of CNTs. Back-gate field effect transistors were demonstrated with the laterally aligned CNTs. The on/off ratios in all the measured devices are lower than 100 due to the drain leakage current. ©2010 IEEE.

Tuning of the electronic characteristics of ZnO nanowire field effect transistors by proton irradiation.

We demonstrated a controllable tuning of the electronic characteristics of ZnO nanowire field effect transistors (FETs) using a high-energy proton beam. After a short proton irradiation time, the threshold voltage shifted to the negative gate bias direction with an increase in the electrical conductance, whereas the threshold voltage shifted to the positive gate bias direction with a decrease in the electrical conductance after a long proton irradiation time. The electrical characteristics of two different types of ZnO nanowires FET device structures in which the ZnO nanowires are placed on the substrate or suspended above the substrate and photoluminescence (PL) studies of the ZnO nanowires provide substantial evidence that the experimental observations result from the irradiation-induced charges in the bulk SiO(2) and at the SiO(2)/ZnO nanowire interface, which can be explained by a surface-band-bending model in terms of gate electric field modulation. Our study on the proton-irradiation-mediated functionalization can be potentially interesting not only for understanding the proton irradiation effects on nanoscale devices, but also for creating the property-tailored nanoscale devices.

Stepped gate polysilicon thin film transistor for large area power applications

For the first time, we report a new poly-Si stepped gate Thin Film Transistor (SG TFT) on glass. The Density of States extracted from measured I-V characteristics has been used to evaluate the device performance with a two dimensional device simulator. The results show that the three-terminal SG TFT device has a switching speed comparable to a low voltage structure and the high on-current capability of a metal field plate (MFP) TFT and the potential for comparable breakdown characteristics.

Carbon based bottom gate thin film transistor

This paper describes the fabrication and characterization of a carbon based, bottom gate, thin film transistor (TFT). The active layer is formed from highly sp2 bonded nitrogenated amorphous carbon (a-C:N) which is deposited at room temperature using a filtered cathodic vacuum arc technique. The TFT shows p-channel operation. The device exhibits a threshold voltage of 15 V and a field effect mobility of 10-4 cm2 V-1 s-1 . The valence band tail of a-C:N is observed to be much shallower than that of a-Si:H, but does not appear to severely impede the shift of the Fermi level. This may indicate that a significant proportion of the a-C tail states can still contribute to conduction.

Growth and characterization of carbon nanotubes for field-emission-display applications

This paper will report on the production, dimensional control, and characterization of arrays of cold-cathode field emitters based on multiwall carbon nanotubes, suitable for use in large-area field-emission-based displays.

Low on-resistance SOI dual-trench-gate MOSFET

A low specific on-resistance (R-{{\rm on}, {\rm sp}}) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation. The SOI MOSFET features double trenches and dual gates (DTDG SOI): an oxide trench in the drift region, a buried gate inset in the oxide trench, and another trench gate (TG) extended to a buried oxide layer. First, the dual gates form dual conduction channels, and the extended gate widens the vertical conduction area; both of which sharply reduce R-{{\rm on}, {\rm sp}}. Second, the oxide trench folds the drift region in the vertical direction, resulting in a reduced device pitch and R-{{\rm on}, {\rm sp}}. Third, the oxide trench causes multidirectional depletion. This not only enhances the reduced surface field effect and thus reshapes the electric field distribution but also increases the drift doping concentration, leading to a reduced R-{{\rm on}, {\rm sp}} and an improved breakdown voltage (BV). Compared with a conventional SOI lateral Double-diffused metal oxide semiconductor (LDMOS), the DTDG MOSFET increases BV from 39 to 92 V at the same cell pitch or decreases R-{{\rm on}, { \rm sp}} by 77% at the same BV by simulation. Finally, the TG extended synchronously acts as an isolation trench between the high/low-voltage regions in a high-voltage integrated circuit, saving the chip area and simplifying the isolation process. © 2006 IEEE.

Trench insulated gate bipolar transistor - a high power switching device

This paper presents a comprehensive theoretical study of the Trench Insulated Gate Bipolar Transistors (TIGBT). Specific physical and geometrical effects, such as the accumulation layer injection, increased channel density, increased channel charge and transversal electric field modulation are discussed. The potential advantages of the Trench IGBT over its conventional planar variant are highlighted. It is concluded that the Trench IGBT is one of the most promising structures in the area of high voltage MOS-controllable switching devices.