Geometrical properties and turbulent flame speed measurements in stationary premixed V-flames using direct numerical simulation

Three dimensional, fully compressible direct numerical simulations (DNS) of premixed turbulent flames are carried out in a V-flame configuration. The governing equations and the numerical implementation are described in detail, including modifications made to the Navier-Stokes Characteristic Boundary Conditions (NSCBC) to accommodate the steep transverse velocity and composition gradients generated when the flame crosses the boundary. Three cases, at turbulence intensities, u′/sL, of 1, 2, and 6 are considered. The influence of the flame holder on downstream flame properties is assessed through the distributions of the surface-conditioned displacement speed, curvature and tangential strain rates, and compared to data from similarly processed planar flames. The distributions are found to be indistinguishable from planar flames for distances greater than about 17δth downstream of the flame holder, where δth is the laminar flame thermal thickness. Favre mean fields are constructed, and the growth of the mean flame brush is found to be well described by simple Taylor type diffusion. The turbulent flame speed, sT is evaluated from an expression describing the propagation speed of an isosurface of the mean reaction progress variable c̃ in terms of the imbalance between the mean reactive, diffusive, and turbulent fluxes within the flame brush. The results are compared to the consumption speed, sC, calculated from the integral of the mean reaction rate, and to the predictions of a recently developed flame speed model (Kolla et al., Combust Sci Technol 181(3):518-535, 2009). The model predictions are improved in all cases by including the effects of mean molecular diffusion, and the overall agreement is good for the higher turbulence intensity cases once the tangential convective flux of c̃ is taken into account. © 2010 Springer Science+Business Media B.V.

Integrated avalanche diode for 600 v Trench IGBT over-voltage protection

Avalanche multiplication has been one of the major destructive failure mechanisms in IGBTs; in order to avoid operating an IGBT under abnormal conditions, it is desirable to develop peripheral protecting circuits monolithically integrated without compromising the operation and performance of the IGBT. In this paper, a monolithically integrated avalanche diode (D av) for 600V Trench IGBT over-voltage protection is proposed. The mix-mode transient simulation proves the clamping capability of the D av when the IGBT is experiencing over-voltage stress in unclamped inductive switching (UIS) test. The spread of avalanche energy, which prevents hot-spot formation, through the help of the avalanche diode feeding back a large fraction of the avalanche current to a gate resistance (R G) is also explained. © 2011 IEEE.

A fast 600-V Tandem PiN Schottky (TPS) rectifier with ultra-low on-state voltage

The Tandem PiN Schottky (TPS) rectifier features lowly-doped p-layers in both active and termination regions, and is applied in 600-V rating for the first time. In the active region, the Schottky contact is in series connection with a transparent p-layer, leading to a superior forward performance than the conventional diodes. In addition, due to the benefit of moderate hole injection from the p-layer, the TPS offers a better trade-off between the on-state voltage and the switching speed. The active p-layer also helps to stabilise the Schottky contact, and hence the electrical data distributions are more concentrated. Regarding the floating p-layer in the termination region, its purpose is to reduce the peak electric fields, and the TPS demonstrates a high breakdown voltage with a compact termination width, less than 70% of the state-of-the-art devices on the market. Experimental results have shown that the 600-V TPS rectifier has an ultra-low on-state voltage of 0.98 V at 250 A/cm 2, a fast turn-off time of 75 ns by the standard RG1 test (I F=0.5A, I R=1A, and I RR=0.25A) and a breakdown voltage over 720 V. It is noteworthy that the p-layers in the active and termination regions can be formed at no extra cost for the use of self-alignment process. © 2012 IEEE.

200-V lateral superjunction LIGBT on partial SOI

This letter presents a novel lateral superjunction lateral insulated-gate bipolar transistor (LIGBT) in partial silicon-on-insulator (SOI) technology in 0.18-μm partial-SOI (PSOI) high-voltage (HV) process. For an n-type superjunction LIGBT, the p-layer in the superjunction drift region not only helps in achieving uniform electric field distribution but also contributes to the on-state current. The superjunction LIGBT successfully achieves a breakdown voltage (BV) of 210 V with an R dson of 765 mΩ ̇ mm 2. It exhibits half the value of specific on-state resistance R dson and three times higher saturation current (I dsat) for the same BV, compared to a comparable lateral superjunction laterally diffused metal-oxide-semiconductor fabricated in the same technology. It also performs well in higher temperature dc operation with 38.8% increase in R dson at 175°C, compared to the room temperature without any degradation in latch-up performance. To realize this device, it only requires one additional mask layer into X-FAB 0.18-μm PSOI HV process. © 2012 IEEE.