Guided growth of neurons and glia using microfabricated patterns of parylene-C on a SiO2 background.

This paper describes a simple technique for the patterning of glia and neurons. The integration of neuronal patterning to Multi-Electrode Arrays (MEAs), planar patch clamp and silicon based 'lab on a chip' technologies necessitates the development of a microfabrication-compatible method, which will be reliable and easy to implement. In this study a highly consistent, straightforward and cost effective cell patterning scheme has been developed. It is based on two common ingredients: the polymer parylene-C and horse serum. Parylene-C is deposited and photo-lithographically patterned on silicon oxide (SiO(2)) surfaces. Subsequently, the patterns are activated via immersion in horse serum. Compared to non-activated controls, cells on the treated samples exhibited a significantly higher conformity to underlying parylene stripes. The immersion time of the patterns was reduced from 24 to 3h without compromising the technique. X-ray photoelectron spectroscopy (XPS) analysis of parylene and SiO(2) surfaces before and after immersion in horse serum and gel based eluant analysis suggests that the quantity and conformation of proteins on the parylene and SiO(2) substrates might be responsible for inducing glial and neuronal patterning.

Local synthesis and alignment of zinc oxide nanowires in aqueous solution using microheaters

A bottom-up technique for synthesizing transversely suspended zinc oxide nanowires (ZnO NWs) under a zinc nitrate (Zn(NO 3) 2· 6H 2O) and hexamethylenetetramine (HMTA, (CH 2) 6·N 4) solution within a microfabricated device is reported in this paper. The device consists of a microheater which is used to initially create an oxidized ZnO seed layer. ZnO NWs are then locally synthesized by the microheater and electrodes embedded within the devices are used to drive electric field directed horizontal alignment of the nanowires within the device. The entire process is carried out at low temperature. This approach has the potential to considerably simplify the fabrication and assembly of ZnO nanowires on CMOS compatible substrates, allowing for the chemical synthesis to be carried out under near-ambient conditions by locally defining the conditions for nanowire growth on a silicon reactor chip. © 2012 IEEE.

Chemical vapor deposition of nanocrystalline graphene directly on arbitrary high-temperature insulating substrates

Large area uniform nanocrystalline graphene is grown by chemical vapor deposition on arbitrary insulating substrates that can survive ∼1000°C. The as-synthesized graphene is nanocrystalline with a domain size in the order of ∼10 nm. The material possesses a transparency and conductivity similar to standard graphene fabricated by exfoliation or catalysis. A noncatalytic mechanism is proposed to explain the experimental phenomena. The developed technique is scalable and reproducible, compatible with the existing semiconductor technology, and thus can be very useful in nanoelectronic applications such as transparent electronics, nanoelectromechanical systems, as well as molecular electronics. © 2012 IEEE.

Cost-effective 10 Gb/s polymer-based chip-to-chip optical interconnect

Board-level optical links are an attractive alternative to their electrical counterparts as they provide higher bandwidth and lower power consumption at high data rates. However, on-board optical technology has to be cost-effective to be commercially deployed. This study presents a chip-to-chip optical interconnect formed on an optoelectronic printed circuit board that uses a simple optical coupling scheme, cost-effective materials and is compatible with well-established manufacturing processes common to the electronics industry. Details of the link architecture, modelling studies of the link's frequency response, characterisation of optical coupling efficiencies and dynamic performance studies of this proof-of-concept chip-to-chip optical interconnect are reported. The fully assembled link exhibits a -3 dBe bandwidth of 9 GHz and -3 dBo tolerances to transverse component misalignments of ±25 and ±37 μm at the input and output waveguide interfaces, respectively. The link has a total insertion loss of 6 dBo and achieves error-free transmission at a 10 Gb/s data rate with a power margin of 11.6 dBo for a bit-error-rate of 10 -12. The proposed architecture demonstrates an integration approach for high-speed board-level chip-to-chip optical links that emphasises component simplicity and manufacturability crucial to the migration of such technology into real-world commercial systems. © 2012 The Institution of Engineering and Technology.

Material-Based Construction Site Image Retrieval

The technological advancements in digital imaging, the widespread popularity of digital cameras, and the increasing demand by owners and contractors for detailed and complete site photograph logs have triggered an ever-increasing growth in the rate of construction image data collection, with thousands of images being stored for each project. However, the sheer volume of images and the difficulties in accurately and manually indexing them have generated a pressing need for methods that can index and retrieve images with minimal or no user intervention. This paper reports recent developments from research efforts in the indexing and retrieval of construction site images in architecture, engineering, construction, and facilities management image database systems. The limitations and benefits of the existing methodologies will be presented, as well as an explanation of the reasons for the development of a novel image retrieval approach that not only can recognize construction materials within the image content in order to index images, but also can be compatible with existing retrieval methods, enabling enhanced results.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. © 2012 Tan et al.

Brillouin scattering of cluster-assembled carbon films

The low frequency vibrational spectrum of cluster beam deposited carbon films was studied by Brillouin light scattering. In thin films the values of both bulk modulus and shear modulus has been estimated from the shifts of surface phonon peaks. The values found indicate a mainly sp2 coordinated random network with low density. In thick films a bulk longitudinal phonon peak was detected in a spectral range compatible with the value of the index of refraction and of the elastic constants of thin films. High surface roughness, combined with a rather strong bulk central peak, prevented the observation of surface phonon features. © 1998 Elsevier Science Ltd. All rights reserved.

The lateral superjunction PSOI LIGBT and LDMOSFET

This paper presents a comparison between the superjunction LIGBT and the LDMOSFET in partial silicon-on-insulator (PSOI) technology in 0.18μm PSOI HV process. The superjunction drift region helps in achieving uniform electric field distribution in both structures but also contributes to the on-state current in the LIGBT. The superjunction LIGBT successfully achieves breakdown voltage (BV) of 210V with Rdson of 765mΩ.mm2. It exhibits reduced specific on-state resistance Rdson and higher saturation current (Idsat) for the same BV compared to a compatible lateral superjunction LDMOS in the same technology. © 2012 IEEE.

Geometry of Miura-folded metamaterials.

This paper describes two folded metamaterials based on the Miura-ori fold pattern. The structural mechanics of these metamaterials are dominated by the kinematics of the folding, which only depends on the geometry and therefore is scale-independent. First, a folded shell structure is introduced, where the fold pattern provides a negative Poisson's ratio for in-plane deformations and a positive Poisson's ratio for out-of-plane bending. Second, a cellular metamaterial is described based on a stacking of individual folded layers, where the folding kinematics are compatible between layers. Additional freedom in the design of the metamaterial can be achieved by varying the fold pattern within each layer.

Investigation of fluorine three-dimensional redistribution during solid-phase-epitaxial-regrowth of amorphous Si

The fluorine redistribution during partial solid-phase-epitaxial-regrowth at 650°C of a preamorphized Si substrate implanted by F was investigated by atom probe tomography (APT), transmission electron microscopy, and secondary ions mass spectrometry. Three-dimensional spatial distribution of F obtained by APT provides a direct observation of F-rich clusters with a diameter of less than 1.5 nm. Density variation compatible with cavities and F-rich molecular ions in correspondence of clusters are in accordance with cavities filled by SiF 4 molecules. Their presence only in crystalline Si while they are not revealed by statistical analysis in amorphous suggests that they form at the amorphous/crystal interface. © 2012 American Institute of Physics.

Energy recycling from multigigahertz clocks using fully integrated switching converters

Large digital chips use a significant amount of energy to broadcast a low-skew, multigigahertz clock to millions of latches located throughout the chip. Every clock cycle, the large aggregate capacitance of the clock network is charged from the supply and then discharged to ground. Instead of wasting this stored energy, it is possible to recycle the energy by controlling its delivery to another part of the chip using an on-chip dc-dc converter. The clock driver and switching converter circuits share many compatible characteristics that allow them to be merged into a single design and fully integrated on-chip. Our buck converter prototype, manufactured in 90-nm CMOS, provides a proof-of-concept that clock network energy can be recycled to other parts of the chip, thus lowering overall energy consumption. It also confirms that monolithic multigigahertz switching converters utilizing zero-voltage switching can be implemented in deep-submicrometer CMOS. With multigigahertz operation, fully integrated inductors and capacitors use a small amount of chip area with low losses. Combining the clock driver with the power converter can share the large MOSFET drivers necessary as well as being energy and space efficient. We present an analysis of the losses which we confirm by experimentally comparing the merged circuit with a conventional clock driver. © 2012 IEEE.

Characterization and fabrication of zinc oxide nanowire devices

In this paper, we demonstrate an approach for the local synthesis of ZnO nanowires (ZnO NWs) and the potential for such structures to be incorporated into device applications. Three network ZnO NW devices are fabricated on a chip by using a bottom-up synthesis approach. Microheaters (defined by standard semiconductor processing) are used to synthesize the ZnO NWs under a zinc nitrate (Zn(NO3)2·6H2O) and hexamethylenetetramine (HMTA, (CH2)6·N4) solution. By controlling synthesis parameters, varying densities of networked ZnO NWs are locally synthesized on the chip. The fabricated networked ZnO NW devices are then characterized using UV excitation and cyclic voltammetry (CV) experiments to measure their photoresponse and electrochemical properties. The experimental results show that the techniques and material systems presented here have the potential to address interesting device applications using fabrication methods that are fully compatible with standard semiconductor processing. © 2013 IEEE.

Slowness: an objective for spike-timing-dependent plasticity?

Our nervous system can efficiently recognize objects in spite of changes in contextual variables such as perspective or lighting conditions. Several lines of research have proposed that this ability for invariant recognition is learned by exploiting the fact that object identities typically vary more slowly in time than contextual variables or noise. Here, we study the question of how this "temporal stability" or "slowness" approach can be implemented within the limits of biologically realistic spike-based learning rules. We first show that slow feature analysis, an algorithm that is based on slowness, can be implemented in linear continuous model neurons by means of a modified Hebbian learning rule. This approach provides a link to the trace rule, which is another implementation of slowness learning. Then, we show analytically that for linear Poisson neurons, slowness learning can be implemented by spike-timing-dependent plasticity (STDP) with a specific learning window. By studying the learning dynamics of STDP, we show that for functional interpretations of STDP, it is not the learning window alone that is relevant but rather the convolution of the learning window with the postsynaptic potential. We then derive STDP learning windows that implement slow feature analysis and the "trace rule." The resulting learning windows are compatible with physiological data both in shape and timescale. Moreover, our analysis shows that the learning window can be split into two functionally different components that are sensitive to reversible and irreversible aspects of the input statistics, respectively. The theory indicates that irreversible input statistics are not in favor of stable weight distributions but may generate oscillatory weight dynamics. Our analysis offers a novel interpretation for the functional role of STDP in physiological neurons.

Modeling of soft clays response for seismic triggering of submarine slides

Submarine landslides pose considerable hazards to coastal communities and offshore structures. The difficulty and cost of obtaining undisturbed samples of offshore soils for determining material properties required for slope stability analyses contribute to the complexity of the problem. There are significant advantages in using a simplified model for the seismic response of submarine slopes, compatible with the limited amount of information that can be realistically gathered, but still able to capture the key elements of clay behavior. This paper illustrates the process of parameter determination and calibration of the SIMPLE DSS model, developed for the study of seismic triggering of submarine slope instabilities. The selection of parameters and predictions of monotonic and cyclic simple shear response are carried out for Boston Blue Clay, a marine clay extensively studied and with a large experimental database available in the literature. The results show that the simplified model is able to reproduce the important trends in the response of the soil, especially in accounting for the effect of the slope.

III-V semiconductor nanowires for optoelectronic device applications

Semiconductor nanowires have recently emerged as a new class of materials with significant potential to reveal new fundamental physics and to propel new applications in quantum electronic and optoelectronic devices. Semiconductor nanowires show exceptional promise as nanostructured materials for exploring physics in reduced dimensions and in complex geometries, as well as in one-dimensional nanowire devices. They are compatible with existing semiconductor technologies and can be tailored into unique axial and radial heterostructures. In this contribution we review the recent efforts of our international collaboration which have resulted in significant advances in the growth of exceptionally high quality IIIV nanowires and nanowire heterostructures, and major developments in understanding the electronic energy landscapes of these nanowires and the dynamics of carriers in these nanowires using photoluminescence, time-resolved photoluminescence and terahertz conductivity spectroscopy. © 2011 Elsevier Ltd. All rights reserved.