TRANSIENT SCANNING ELECTRON BEAM ANNEALING METHODS USED TO STUDY DIFFUSION AND DEFECTS IN IMPLANTED SILICON.

Rapid thermal annealing of arsenic and boron difluoride implants, such as those used for source/drain regions in CMOS, has been carried out using a scanning electron beam annealer, as part of a study of transient diffusion effects. Three types of e-beam anneal have been performed, with peak temperatures in the range 900 -1200 degree C; the normal isothermal e-beam anneals, together with sub-second fast anneals and 'dual-pulse' anneals, in which the sample undergoes an isothermal pre-anneal followed by rapid heating to the required anneal temperature is less than 0. 5s. The diffusion occuring during these anneal cycles has been modelled using SPS-1D, an implant and diffusion modelling program developed by one of the authors. This has been modified to incorporate simulated temperature vs. time cycles for the anneals. Results are presented applying the usual equilibrium clustering model, a transient point-defect enhancement to the diffusivity proposed recently by Fair and a new dynamic clustering model for arsenic. Good agreement with SIMS measurements is obtained using the dynamic clustering model, without recourse to a transient defect model.

Conduction bottleneck in silicon nanochain single electron transistors operating at room temperature

Single electron transistors are fabricated on single Si nanochains, synthesised by thermal evaporation of SiO solid sources. The nanochains consist of one-dimensional arrays of ~10nm Si nanocrystals, separated by SiO 2 regions. At 300 K, strong Coulomb staircases are seen in the drain-source current-voltage (I ds-V ds) characteristics, and single-electron oscillations are seen in the drain-source current-gate voltage (I ds-V ds) characteristics. From 300-20 K, a large increase in the Coulomb blockade region is observed. The characteristics are explained using singleelectron Monte Carlo simulation, where an inhomogeneous multiple tunnel junction represents a nanochain. Any reduction in capacitance at a nanocrystal well within the nanochain creates a conduction " bottleneck", suppressing current at low voltage and improving the Coulomb staircase. The single-electron charging energy at such an island can be very high, ~20k BT at 300 K. © 2012 The Japan Society of Applied Physics.

Ferroelectric liquid crystal over silicon devices

Over the past 20 years, ferroelectric liquid crystal over silicon (FLCOS) devices have made a wide impact on applications as diverse as optical correlation and holographic projection. To cover the entire gamut of this technology would be difficult and long winded; hence, this paper describes the significant developments of FLCOS within the Engineering Department at the University of Cambridge.The purpose of this paper is to highlight the key issues in fabricating silicon backplane spatial light modulators (SLMs) and to indicate ways in which the technology can be fabricated using cheap, low-density production and manufacturability. Three main devices have been fabricated as part of several research programmes and are documented in this paper. The fast bitplane SLM and the reconfigurable optical switches for aerospace and telecommunications systems (ROSES) SLM will form the basis of a case study to outline the overall processes involved. There is a great deal of commonality in the fabrication processes for all three devices, which indicates their potential strength and demonstrates that these processes can be made independent of the SLMs that are being assembled. What is described is a generic process that can be applied to any silicon backplane SLM on a die-by-die basis. There are hundreds of factors that can affect the yield in a manufacturing process and the purpose of a good process design procedure is to minimise these factors. One of the most important features in designing a process is fabrication experience, as so many of the lessons in this business can only be learned this way. We are working with the advantage of knowing the mistakes already made in the flat panel display industry, but we are also faced with the fact that those mistakes took many years and many millions of dollars to make.The fabrication process developed here originates and adapts earlier processes from various groups around the world. There are also a few totally new processes that have now been adopted by others in the field. Many, such as the gluing process, are still on-going and have to be worked on more before they will fully suit 'manufacturability'. © 2012 Copyright Taylor and Francis Group, LLC.

Diffraction based phase compensation method for phase-only liquid crystal on silicon devices in operation.

A method to measure the optical response across the surface of a phase-only liquid crystal on silicon device using binary phase gratings is described together with a procedure to compensate its spatial optical phase variation. As a result, the residual power between zero and the minima of the first diffraction order for a binary grating can be reduced by more than 10 dB, from -15.98 dB to -26.29 dB. This phase compensation method is also shown to be useful in nonbinary cases. A reduction in the worst crosstalk by 5.32 dB can be achieved when quantized blazed gratings are used.

SIMPLE REMESHING SCHEME FOR THE FINITE ELEMENT BASED SIMULATION OF DOPANT DIFFUSION IN SILICON.

Process simulation programs are valuable in generating accurate impurity profiles. Apart from accuracy the programs should also be efficient so as not to consume vast computer memory. This is especially true for devices and circuits of VLSI complexity. In this paper a remeshing scheme to make the finite element based solution of the non-linear diffusion equation more efficient is proposed. A remeshing scheme based on comparing the concentration values of adjacent node was then implemented and found to remove the problems of oscillation.

Controllable chemical vapor deposition of large area uniform nanocrystalline graphene directly on silicon dioxide

Metal-catalyst-free chemical vapor deposition (CVD) of large area uniform nanocrystalline graphene on oxidized silicon substrates is demonstrated. The material grows slowly, allowing for thickness control down to monolayer graphene. The as-grown thin films are continuous with no observable pinholes, and are smooth and uniform across whole wafers, as inspected by optical-, scanning electron-, and atomic force microscopy. The sp 2 hybridized carbon structure is confirmed by Raman spectroscopy. Room temperature electrical measurements show ohmic behavior (sheet resistance similar to exfoliated graphene) and up to 13 of electric-field effect. The Hall mobility is ∼40 cm 2/Vs, which is an order of magnitude higher than previously reported values for nanocrystalline graphene. Transmission electron microscopy, Raman spectroscopy, and transport measurements indicate a graphene crystalline domain size ∼10 nm. The absence of transfer to another substrate allows avoidance of wrinkles, holes, and etching residues which are usually detrimental to device performance. This work provides a broader perspective of graphene CVD and shows a viable route toward applications involving transparent electrodes. © 2012 American Institute of Physics.