Fourier spectrum based extraction of an equivalent trap state density in indium gallium zinc oxide transistors

Segregating the dynamics of gate bias induced threshold voltage shift, and in particular, charge trapping in thin film transistors (TFTs) based on time constants provides insight into the different mechanisms underlying TFTs instability. In this Letter we develop a representation of the time constants and model the magnitude of charge trapped in the form of an equivalent density of created trap states. This representation is extracted from the Fourier spectrum of the dynamics of charge trapping. Using amorphous In-Ga-Zn-O TFTs as an example, the charge trapping was modeled within an energy range of ΔEt 0.3 eV and with a density of state distribution as Dt(Et-j)=Dt0exp(-ΔEt/ kT)with Dt0 = 5.02 × 1011 cm-2 eV-1. Such a model is useful for developing simulation tools for circuit design. © 2014 AIP Publishing LLC.

High performance transistors based on the controlled growth of triisopropylsilylethynyl-pentacene crystals via non-isotropic solvent evaporation

Triisopropylsilylethynyl-pentacene (TIPS-PEN) has proven to be one of the most promising small molecules in the field of molecular electronics, due to its unique features in terms of stability, performance and ease of processing. Among a wide variety of well-established techniques for the deposition of TIPS-PEN, blade-metered methods have recently gained great interest towards the formation of uniform crystalline films over a large area. Following this rationale, we herein designed a versatile approach based on blade-coating, which overcomes the problem of anisotropic crystal formation by manipulating the solvent evaporation behaviour, in a way that brings about a preferential degree of crystal orientation. The applicability of this method was evaluated by fabricating field-effect transistors on glass as well as on silicon dioxide/silicon (SiO2/Si) substrates. Interestingly, in an attempt to improve the rheological and wetting behaviour of the liquid films on the SiO2/Si substrates, we introduced a polymeric interlayer of polystyrene (PS) or polymethylmethacrylate (PMMA) which concurrently acts as passivation and crystallization assisting layer. In this case, the synergistic effects of the highly-ordered crystalline structure and the oxide surface modification were thoroughly investigated. The overall performance of the fabricated devices revealed excellent electrical characteristics, with high saturation mobilities up to 0.72 cm2 V-1 s-1 (on glass with polymeric dielectric), on/off current ratio >104 and low threshold voltage values (<-5 V). This journal is © the Partner Organisations 2014.