387 resultados para DC-AC power convertors


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This paper advocates 'reduce, reuse, recycle' as a complete energy savings strategy. While reduction has been common to date, there is growing need to emphasize reuse and recycling as well. We design a DC-DC buck converter to demonstrate the 3 techniques: reduce with low-swing and zero voltage switching (ZVS), reuse with supply stacking, and recycle with regulated delivery of excess energy to the output load. The efficiency gained from these 3 techniques helps offset the loss of operating drivers at very high switching frequencies which are needed to move the output filter completely on-chip. A prototype was fabricated in 0.18μm CMOS, operates at 660MHz, and converts 2.2V to 0.75-1.0V at ∼50mA.1 © 2008 IEEE.

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In this paper, a new thermal model based on the Fourier series solution of heat conduction equation has been introduced in detail. 1-D and 2-D Fourier series thermal models have been programmed in MATLAB/Simulink. Compared with the traditional finite-difference thermal model and equivalent RC thermal network, the new thermal model can provide high simulation speed with high accuracy, which has been proved to be more favorable in dynamic thermal characterization on power semiconductor switches. The complete electrothermal simulation models of insulated gate bipolar transistor (IGBT) and power diodes under inductive load switching condition have been successfully implemented in MATLAB/Simulink. The experimental results on IGBT and power diodes with clamped inductive load switching tests have verified the new electrothermal simulation model. The advantage of Fourier series thermal model over widely used equivalent RC thermal network in dynamic thermal characterization has also been validated by the measured junction temperature.© 2010 IEEE.

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Compact fluorescent lamps (CFLs) incorporating electronic ballasts are widely used in lighting. In many cases, the ability to dim the lamp is a requirement. Dimming can be achieved by varying the switching frequency of the inverter or by changing the voltage supplied to the inverter. The effect of dimming by both approaches on the power losses in the inverter is studied in this work. The lamp and associated inverter has been modeled in Pspice, using a behavioral model for the CFL. Predicted losses are in good agreement with experimental data obtained from calorimetry. After verification, the model was then used to determine the distribution of losses within the inverter, enabling a comparison of the effects of the two dimming methods to be made. © 2011 IEEE.

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An analytical model for the electric field and the breakdown voltage (BV) of an unbalanced superjunction (SJ) device is presented in this paper. The analytical technique uses a superposition approach treating the asymmetric charge in the pillars as an excess charge component superimposed on a balanced charge component. The proposed double-exponentialmodel is able to accurately predict the electric field and the BV for unbalanced SJ devices in both punch through and non punch through conditions. The model is also reasonably accurate at extremely high levels of charge imbalance when the devices behave similarly to a PiN diode or to a high-conductance layer. The analytical model is compared against numerical simulations of charge unbalanced SJ devices and against experimental results. © 2009 IEEE.

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This paper presents a comprehensive theoretical study of the Trench Insulated Gate Bipolar Transistors (TIGBT). Specific physical and geometrical effects, such as the accumulation layer injection, increased channel density, increased channel charge and transversal electric field modulation are discussed. The potential advantages of the Trench IGBT over its conventional planar variant are highlighted. It is concluded that the Trench IGBT is one of the most promising structures in the area of high voltage MOS-controllable switching devices.

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Power allocation is studied for fixed-rate transmission over block-fading channels with arbitrary continuous fading distributions and perfect transmitter and receiver channel state information. Both short- and long-term power constraints for arbitrary input distributions are considered. Optimal power allocation schemes are shown to be direct applications of previous results in the literature. It is shown that the short- and long-term outage exponents for arbitrary input distributions are related through a simple formula. The formula is useful to predict when the delay-limited capacity is positive. Furthermore, this characterization is useful for the design of efficient coding schemes for this relevant channel model. © 2010 IEEE.

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The first monolithically integrated 44 switch with power monitoring function using on-chip PIN photodiodes is reported. Using 10Gb/s signals, under active power control an IPDR of 12dB for a 1dB power penalty is achieved. © 2012 OSA.

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Theoretical investigations have been carried out to analyze and compare the link power budget and power dissipation of non-return-to-zero (NRZ), pulse amplitude modulation-4 (PAM-4), carrierless amplitude and phase modulation-16 (CAP-16) and 16-quadrature amplitude modulation-orthogonal frequency division multiplexing (16-QAM-OFDM) systems for data center interconnect scenarios. It is shown that for multimode fiber (MMF) links, NRZ modulation schemes with electronic equalization offer the best link power budget margins with the least power dissipation for short transmission distances up to 200 m; while OOFDM is the only scheme which can support a distance of 300 m albeit with power dissipation as high as 4 times that of NRZ. For short single mode fiber (SMF) links, all the modulation schemes offer similar link power budget margins for fiber lengths up to 15 km, but NRZ and PAM-4 are preferable due to their system simplicity and low power consumption. For lengths of up to 30 km, CAP-16 and OOFDM are required although the schemes consume 2 and 4 times as much power respectively compared to that of NRZ. OOFDM alone allows link operation up to 35 km distances. © 1983-2012 IEEE.

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A finite element model for a YBCO pancake coil with a magnetic substrate is developed in this paper. An axial symmetrical H formulation and the E-J power law are used to construct the model, with the magnetic substrate considered by introducing an extra time-dependent term in the formula. A pancake coil is made and tested. The measurement of critical current and transport loss is compared to the model result, showing good consistency. The influence of magnetic substrate in the condition of AC and DC current is studied. The AC loss decreases without a magnetic substrate. It is observed that when the applied DC current approaches the critical current the coil turn loss profile changes completely in the presence of magnetic substrate due to the change of magnetic field distribution. © 2012 IOP Publishing Ltd.

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This paper presents the design of an AC loss experiment using nitrogen boil-off method. This experiment is aimed at exploring the AC loss of HTS double race-track coils which will be installed on the rotor of a wind turbine generator. The operating environment is simulated by designing a cryostat with rotating magnetic field windings. Apart from the fact that the alternating magnetic field causes most of AC loss on the HTS coils, we also believe that the DC background field would be another important factor causing AC loss if the HTS coil is experiencing by both alternating magnetic field in the perpendicular direction and DC background field in the parallel direction. In order to perform the boil-off measurement, we present the method to estimate the heat leakage in the cryostat which might cause errors to the measurement. © 2011 IEEE.

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This paper presents the steps and the challenges for implementing analytical, physics-based models for the insulated gate bipolar transistor (IGBT) and the PIN diode in hardware and more specifically in field programmable gate arrays (FPGAs). The models can be utilised in hardware co-simulation of complex power electronic converters and entire power systems in order to reduce the simulation time without compromising the accuracy of results. Such a co-simulation allows reliable prediction of the system's performance as well as accurate investigation of the power devices' behaviour during operation. Ultimately, this will allow application-specific optimisation of the devices' structure, circuit topologies as well as enhancement of the control and/or protection schemes.

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With series insulated-gate bipolar transistor (IGBT) operation, well-matched gate drives will not ensure balanced dynamic voltage sharing between the switching devices. Rather, it is IGBT parasitic capacitances, mainly gate-to-collector capacitance Cgc, that dominate transient voltage sharing. As Cgc is collector voltage dependant and is significantly larger during the initial turn-off transition, it dominates IGBT dynamic voltage sharing. This paper presents an active control technique for series-connected IGBTs that allows their dynamic voltage transition dV\ce/dt to adaptively vary. Both switch ON and OFF transitions are controlled to follow a predefined dVce/dt. Switching losses associated with this technique are minimized by the adaptive dv /dt control technique incorporated into the design. A detailed description of the control circuits is presented in this paper. Experimental results with up to three series devices in a single-ended dc chopper circuit, operating at various low voltage and current levels, are used to illustrate the performance of the proposed technique. © 2012 IEEE.

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High-power converters usually need longer dead-times than their lower-power counterparts and a lower switching frequency. Also due to the complicated assembly layout and severe variations in parasitics, in practice the conventional dead-time specific adjustment or compensation for high-power converters is less effective, and usually this process is time-consuming and bespoke. For general applications, minimising or eliminating dead-time in the gate drive technology is a desirable solution. With the growing acceptance of power electronics building blocks (PEBB) and intelligent power modules (IPM), gate drives with intelligent functions are in demand. Smart functions including dead time elimination/minimisation can improve modularity, flexibility and reliability. In this paper, a dead-time minimisation using Active Voltage Control (AVC) gate drive is presented. © 2012 IEEE.