Potential tuning of porous silicon luminescence

Electrochemical investigations were conducted of the effect of potential on the luminescence of porous silico (PS). The use of liquid contacts allows the potential to be controlled during studies of the photoluminescence (PL) and electroluminescence (EI). The PL and EL of PS samples prepared from n-type substrates is considered. To obtain luminescence from such PS it is necessary to generate holes in the valence band. This is achieved by either photoexcitation or an electrochemical process involving the reduction of persulfate. This paper describes the investigations of the effect of potential on the PL and EL of PS. A mechanism of 'potential tuning' based on electron occupancy and Auger quenching is then proposed.

Analytic model for turn off in the silicon-on-insulator LIGBT

Lateral insulated gate bipolar transistors (LIGBTs) in silicon-on-insulator (SOI) show a unique turn off characteristic when compared to junction-isolated RESURF LIGBTs or vertical IGBTs. The turn off characteristic shows an extended `terrace' where, after the initial fast transient characteristic of IGBTs due to the loss of the electron current, the current stays almost at the same value for an extended period of time, before suddenly dropping to zero. In this paper, we show that this terrace arises because there is a value of LIGBT current during switch off where the rate of expansion of the depletion region with respect to the anode current is infinite. Once this level of anode current is approached, the depletion region starts to expand very rapidly, and is only stopped when it reaches the n-type buffer layer surrounding the anode. Once this happens, the current rapidly drops to zero. A quasi-static analytic model is derived to explain this behaviour. The analytically modelled turn off characteristic agrees well with that found by numerical simulation.

Hydrogenated amorphous silicon and silicon nitride deposited at less than 100° C by ECR-PECVD for thin film transistors

A systematic study has been made of the growth of both hydrogenated amorphous silicon (a-Si:H) and silicon nitride (a-SiN) by electron cyclotron resonance plasma enhanced chemical vapour deposition (ECR-PECVD). In the case of a-SiN, helium and nitrogen gas is injected into the system such that it passes through the resonance zone. These highly ionised gases provide sufficient energy to ionise the silane gas, which is injected further downstream. It is demonstrated that a gas phase reaction occurs between the silane and nitrogen species. It is control of the ratio of silane to nitrogen in the plasma which is critical for the production of stoichiometric a-SiN. Material has been produced at 80°C with a Si:N ratio of 1:1.3 a breakdown strength of ∼6 MV cm-1 and resistivity of > 1014 Ω cm. In the case of a-Si:H, helium and hydrogen gas is injected into the ECR zone and silane is injected downstream. It is shown that control of the gas phase reactions is critical in this process also. a-Si:H has been deposited at 80 °C with a dark conductivity of 10-11 Ω-1 cm-1 and a photosensitivity of justbelowl 4×104. Such materials are suitable for use in thin film transistors on plastic substrates.

PHOTOENHANCED DEPOSITION OF HYDROGENATED AMORPHOUS SILICON THIN FILMS.

This paper will review the different U. V. lamp photo-CVD (Chemical Vapor Deposition) techniques which have been utilized for the production of highly photoconductive hydrogenated amorphous silicon (a-Si:H) thin films. Most of these require the transmission of U. V. light through a window into the reaction vessel; leading to unwanted U. V. light absorption by the window and the a-Si:H film which tends to form on its inner surface. A deposition system developed in our laboratory will also be described, which circumvents these problems by incorporating a windowless discharge lamp into the reaction vessel.

Characterization of defect removal in hydrogenated and deuterated amorphous silicon thin film transistors

Thin film transistors (TFTs) utilizing an hydrogenated amorphous silicon (a-Si:H) channel layer exhibit a shift in the threshold voltage with time under the application of a gate bias voltage due to the creation of metastable defects. These defects are removed by annealing the device with zero gate bias applied. The defect removal process can be characterized by a thermalization energy which is, in turn, dependent upon an attempt-to-escape frequency for defect removal. The threshold voltage of both hydrogenated and deuterated amorphous silicon (a-Si:D) TFTs has been measured as a function of annealing time and temperature. Using a molecular dynamics simulation of hydrogen and deuterium in a silicon network in the H2 * configuration, it is shown that the experimental results are consistent with an attempt-to-escape frequency of (4.4 ± 0.3) × 1013 Hz and (5.7 ± 0.3) × 1013 Hz for a-Si:H and a-Si:D respectively which is attributed to the oscillation of the Si-H and Si-D bonds. Using this approach, it becomes possible to describe defect removal in hydrogenated and deuterated material by the thermalization energies of (1.552 ± 0.003) eV and (1.559 ± 0.003) eV respectively. This correlates with the energy per atom of the Si-H and Si-D bonds. © 2006 Elsevier B.V. All rights reserved.

How to achieve high mobility thin film transistors by direct deposition of silicon using 13.56 MHz RF PECVD?

CMOS nanocrystalline silicon thin film transistors with high field effect mobility are reported. The transistors were directly deposited by radio-frequency plasma enhanced chemical vapor deposition at 150°C The transistors show maximum field effect mobility of 450 cm2/V-s for electrons and 100 cm2/V-s for holes at room temperature. We attribute the high mobilities to a reduction of the oxygen content, which acts as an accidental donor. Indeed, secondary ion mass spectrometry measurements show that the impurity concentration in the nanocrystalline Si layer is comparable to, or lower than, the defect density in the material, which is already low thanks to hydrogen passivation.

The silicon backplane design for an LCOS polarization-insensitive phase hologram SLM

Polarization-insensitivity is achieved in a reflective spatial light modulator by laying a quarter-wave plate (QWP) at the incident wavelength directly over the mirror pixels of a silicon backplane, and forming a nematle Fréedrickcz cell over the QWP to modulate the reflected phase. To achieve the highest drive voltage from the available silicon process, a switched voltage common front electrode design is described, with variable amplitude square wave drive to the pixels to maintain constant root-mean-square drive and minimize phase fluctuations during the dc balance refresh cycle. The silicon has been fabricated and liquid-crystal-on-silicon cells both with and without the QWP assembled; applications include optically transparent switches for optical networks, beam steering for add-drop multiplexers for wavelength-division- multiplexing telecommunications, television multicast, and holographic projection.

A packaging technique for silicon MEMS strain sensors on steel

A packaging technique suited to applying MEMS strain sensors realized on a silicon chip to a steel flat surface is described. The method is based on adhesive bonding of the silicon chip rear surface on steel using two types of glue normally used for standard piezoresistive strain sensors (Mbond200/ 600), using direct wire bonding of the chip to a Printed Circuit Board, also fixed on steel. In order to protect the sensor from the external environment, and to improve the MEMS performance, the silicon chip is encapsulated with a metal cap hermetically sealed-off under vacuum condition with a vacuum adhesive in which the bonding wires are also protected from possible damage. In order to evaluate the mechanical coupling of the silicon chip with the bar and thestress transfer extent to the silicon surface, commercial strain sensors have been applied on the chip glued on a steel bar in alaboratory setup able to generate strain by inflection, yielding a stress transfer around 70% from steel to silicon. © 2008 IEEE.

Amorphous silicon display backplanes on plastic substrates

Amorphous silicon thin-film transistors and pixel driver circuits for organic light-emitting diode displays have been fabricated on plastic substrates. Pixel circuits demonstrate sufficient current delivery and long-term stable operation. © 2005 IEEE.

High mobility N-channel and P-channel nanocrystalline silicon thin-film transistors

We report high hole and electron mobilities in nanocrystalline silicon (nc-Si:H) top-gate staggered thin-film transistors (TFTs) fabricated by direct plasma-enhanced chemical vapor deposition (PECVD) at 260°C. The n-channel nc-Si:H TFT with n+ nc-Si:H ohmic contacts shows a field-effect electron mobility (μnFE) of 130 cm2/Vs, which increases to 150 cm2/Vs with Cr-silicide contacts, along with a field-effect hole mobility (μhFE) of 25 cm2/Vs. To the best of our knowledge, the hole and electron mobilities reported here are the highest achieved to date using direct PECVD. © 2005 IEEE.

Enhanced reflection from arrays of silicon based inverted nanocones

We report enhanced reflection displayed by arrays of silicon based inverted nanocones. Theoretical studies suggest that such arrays display enhanced reflection and photonic band gaps within the optical and near infrared regions. Measured results show three to four fold enhancement in reflection and agree well with calculations. Such arrays can be used to enhance infrared reflection in photovoltaic devices which mostly contribute towards heating. © 2011 American Institute of Physics.