Substrate-assisted nucleation of ultra-thin dielectric layers on graphene by atomic layer deposition

We report on a large improvement in the wetting of Al 2O 3 thin films grown by un-seeded atomic layer deposition on monolayer graphene, without creating point defects. This enhanced wetting is achieved by greatly increasing the nucleation density through the use of polar traps induced on the graphene surface by an underlying metallic substrate. The resulting Al 2O 3/graphene stack is then transferred to SiO 2 by standard methods. © 2012 American Institute of Physics.

A comparative study of plasma-enhanced chemical vapor gate dielectrics for solution-processed polymer thin-film transistor circuit integration

This paper considers plasma-enhanced chemical vapor deposited (PECVD) silicon nitride (SiNx) and silicon oxide (SiOx) as gate dielectrics for organic thin-film transistors (OTFTs), with solution-processed poly[5, 5′ -bis(3-dodecyl-2-thienyl)-2, 2′ -bithiophene] (PQT-12) as the active semiconductor layer. We examine transistors with SiNx films of varying composition deposited at 300 °C as well as 150 °C for plastic compatibility. The transistors show over 100% (two times) improvement in field-effect mobility as the silicon content in SiNx increases, with mobility (μFE) up to 0.14 cm2 /V s and on/off current ratio (ION / IOFF) of 108. With PECVD SiOx gate dielectric, preliminary devices exhibit a μFE of 0.4 cm2 /V s and ION / IOFF of 108. PQT-12 OTFTs with PECVD SiNx and SiOx gate dielectrics on flexible plastic substrates are also presented. These results demonstrate the viability of using PECVD SiN x and SiOx as gate dielectrics for OTFT circuit integration, where the low temperature and large area deposition capabilities of PECVD films are highly amenable to integration of OTFT circuits targeted for flexible and lightweight applications. © 2008 American Institute of Physics.

Cross-sectional structure of tetrahedral amorphous carbon thin films

A cross-sectional transmission electron microscope study of the low density layers at the surface and at the substrate-film interface of tetrahedral amorphous carbon (ta-C) films grown on (001) silicon substrates is presented. Spatially resolved electron energy loss spectroscopy is used to determine the bonding and composition of a tetrahedral amorphous carbon film with nanometre spatial resolution. For a ta-C film grown with a substrate bias of -300 V, an interfacial region approximately 5 nm wide is present in which the carbon is sp2 bonded and is mixed with silicon and oxygen from the substrate. An sp2 bonded layer observed at the surface of the film is 1.3 ± 0.3 nm thick and contains no detectable impurities. It is argued that the sp2 bonded surface layer is intrinsic to the growth process, but that the sp2 bonding in the interfacial layer at the substrate may be related to the presence of oxygen from the substrate.

Amorphous carbon for use in thin film transistors

Tetrahedrally bonded amorphous carbon (ta-C) is a new type of semiconducting thin film material. It can be produced at room temperature using the Filtered Cathodic Vacuum Arc technique. The as-grown undoped ta-C is p-type in nature but it can be n-doped by the addition of nitrogen during deposition. This paper will describe thin film transistor design and fabrication using ta-C as the active channel layer.

Carbon based bottom gate thin film transistor

This paper describes the fabrication and characterization of a carbon based, bottom gate, thin film transistor (TFT). The active layer is formed from highly sp2 bonded nitrogenated amorphous carbon (a-C:N) which is deposited at room temperature using a filtered cathodic vacuum arc technique. The TFT shows p-channel operation. The device exhibits a threshold voltage of 15 V and a field effect mobility of 10-4 cm2 V-1 s-1 . The valence band tail of a-C:N is observed to be much shallower than that of a-Si:H, but does not appear to severely impede the shift of the Fermi level. This may indicate that a significant proportion of the a-C tail states can still contribute to conduction.

Influence of the state of the inlet endwall boundary layer on the interaction between pressure surface separation and endwall flows

This paper describes the effect of the state of the inlet boundary layer (laminar or turbulent) on the structure of the endwall flow on two different profiles of low-pressure (LP) turbine blades (solid thin and hollow thick). At present the state of the endwall boundary layer at the inlet of a real LP turbine is not known. The intention of this paper is to show that, for different designs of LP turbine, the state of the inlet boundary layer affects the performance of the blade in very different ways. The testing was completed at low speed in a linear cascade using area traversing, flow visualization and static pressure measurements. The paper shows that, for a laminar inlet boundary layer, the two profiles have a similar loss distribution and structure of endwall flow. However, for a turbulent inlet boundary layer the two profiles are shown to differ significantly in both the total loss and endwall flow structure. The pressure side separation bubble on the solid thin profile is shown to interact with the passage vortex, causing a higher endwall loss than that measured on the hollow thick profile.

Characterization of defect removal in hydrogenated and deuterated amorphous silicon thin film transistors

Thin film transistors (TFTs) utilizing an hydrogenated amorphous silicon (a-Si:H) channel layer exhibit a shift in the threshold voltage with time under the application of a gate bias voltage due to the creation of metastable defects. These defects are removed by annealing the device with zero gate bias applied. The defect removal process can be characterized by a thermalization energy which is, in turn, dependent upon an attempt-to-escape frequency for defect removal. The threshold voltage of both hydrogenated and deuterated amorphous silicon (a-Si:D) TFTs has been measured as a function of annealing time and temperature. Using a molecular dynamics simulation of hydrogen and deuterium in a silicon network in the H2 * configuration, it is shown that the experimental results are consistent with an attempt-to-escape frequency of (4.4 ± 0.3) × 1013 Hz and (5.7 ± 0.3) × 1013 Hz for a-Si:H and a-Si:D respectively which is attributed to the oscillation of the Si-H and Si-D bonds. Using this approach, it becomes possible to describe defect removal in hydrogenated and deuterated material by the thermalization energies of (1.552 ± 0.003) eV and (1.559 ± 0.003) eV respectively. This correlates with the energy per atom of the Si-H and Si-D bonds. © 2006 Elsevier B.V. All rights reserved.

How to achieve high mobility thin film transistors by direct deposition of silicon using 13.56 MHz RF PECVD?

CMOS nanocrystalline silicon thin film transistors with high field effect mobility are reported. The transistors were directly deposited by radio-frequency plasma enhanced chemical vapor deposition at 150°C The transistors show maximum field effect mobility of 450 cm2/V-s for electrons and 100 cm2/V-s for holes at room temperature. We attribute the high mobilities to a reduction of the oxygen content, which acts as an accidental donor. Indeed, secondary ion mass spectrometry measurements show that the impurity concentration in the nanocrystalline Si layer is comparable to, or lower than, the defect density in the material, which is already low thanks to hydrogen passivation.

Metastability mechanisms in thin film transistors quantitatively resolved using post-stress relaxation of threshold voltage

A new approach is presented to resolve bias-induced metastability mechanisms in hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs). The post stress relaxation of threshold voltage (V(T)) was employed to quantitatively distinguish between the charge trapping process in gate dielectric and defect state creation in active layer of transistor. The kinetics of the charge de-trapping from the SiN traps is analytically modeled and a Gaussian distribution of gap states is extracted for the SiN. Indeed, the relaxation in V(T) is in good agreement with the theory underlying the kinetics of charge de-trapping from gate dielectric. For the TFTs used in this work, the charge trapping in the SiN gate dielectric is shown to be the dominant metastability mechanism even at bias stress levels as low as 10 V.

Dual gate photo-thin film transistor with high photoconductive gain for high reliability, and low noise flat panel transparent imager

In this presentation, we report excellent electrical and optical characteristics of a dual gate photo thin film transistor (TFT) with bi-layer oxide channel, which was designed to provide virgin threshold voltage (V T) control, improve the negative bias illumination temperature stress (NBITS) reliability, and offer high photoconductive gain. In order to address the photo-sensitivity of phototransistor for the incoming light, top transparent InZnO (IZO) gate was employed, which enables the independent gate control of dual gate photo-TFT without having any degradation of its photosensitivity. Considering optimum initial V T and NBITS reliability for the device operation, the top gate bias was judiciously chosen. In addition, the speed and noise performance of the photo-TFT is competitive with silicon photo-transistors, and more importantly, its superiority lies in optical transparency. © 2011 IEEE.

Tests for conceptual design of 6.6 kV class superconducting fault current limiter with YBCO thin film elements

A superconducting fault current limiter (SFCL) for 6.6 kV and 400 A installed in a cubicle for a distribution network substation was conceptually designed. The SFCL consists of parallel- and series-connected superconducting YBCO elements and a limiting resistor. Before designing the SFCL, some tests were carried out. The width and length of each element used in the tests are 30 mm and 210 mm, respectively. The element consists of YBCO thin film of about 200 nm in thickness on cerium dioxide (CeO2) as a cap-layer on a sapphire substrate by metal-organic deposition with a protective metal coat. In the tests, characteristics of each element, such as over-current, withstand-voltage, and so on, were obtained. From these characteristics, series and parallel connections of the elements, called units, were considered. The characteristics of the units were obtained by tests. From the test results, a single phase prototype SFCL was manufactured and tested. Thus, an SFCL rated at 6.6 kV and 400 A can be designed. © 2009 IEEE.

On optical reflection at heterojunction interface of thin film solar cells

Heterojunction is an important structure for the development of photovoltaic solar cells. In contrast to homojunction structures, heterojunction solar cells have internal crystalline interfaces, which will reflect part of the incident light, and this has not been considered carefully before though many heterostructure solar cells have been commercialized. This paper discusses the internal reflection for various material systems used for the development of heterostructure-based solar cells. It has been found that the most common heterostructure solar cells have internal reflection less than 2%, while some potential heterojunction solar cells such as ITO/GaAs, ITO/InP, Si/Ge, polymer/semiconductors and oxide semiconductors may have internal reflection as high as 20%. Also it is worse to have a window layer with a lower refractive index than the absorption layer for solar cells. Ignoring this strong internal reflection will lead to severe deterioration and reduction of conversion efficiency; therefore measures have to be taken to minimize or prevent this internal reflection. © 2013 Elsevier B.V.