Directly modulated wavelength-multiplexed integrated microring laser array

The first demonstration of a directly modulated microring laser array is presented for on-off keyed, wavelength- division- multiplexed fiber-optic data transmission. GaInAsP-InP microring resonators oscillating at separate wavelengths in the 1.5-μm band are vertically coupled to a common passive waveguide bus, which is fabricated on the reverse side of the InP membrane. Two microrings defined with radii for a wavelength channel separation of 6 nm have been assessed for both individual and simultaneous operation. Negligible power penalty (<0.2 dB) is observed for wavelength-division-multiplexed operation with and without transmission over a 25-km fiber span in a manner which indicates low crosstalk between the integrated sources. A device area of less than 0.12 mm2 per microring on a common passive bus allows a highly scalable solution for short-reach wavelength-multiplexed links. © 2008 IEEE.

Deposition of diamond-like carbon films by photon-enhanced chemical vapour deposition of methane using a windowless hydrogen lamp

Thin films of diamond-like carbon (DLC) have been deposited using a novel photon-enhanced chemical vapour deposition (photo-CVD) method. This low energy method may be a way to produce better interfaces in electronic devices by reducing damage due to ion bombardment. Methane requires high energy photons for photolysis to take place and these are not transmitted in most photo-CVD methods owing to the presence of a window between the lamp and the deposition environment. In our photo-CVD system there is no window and all the high energy photons are transmitted into the reaction gas. Initial work has proved promising and this paper presents recent results. Films have been characterized by measuring electron energy loss spectra, by ellipsometry and by fabricating and testing diode structures. Results indicate that the films are of a largely amorphous nature and are semiconducting. Diode structures have on/off current ratios of up to 106.

Short-channel polymer field-effect-transistor fabrication using spin-coating-induced edge template and ink-jet printing

A method to fabricate polymer field-effect transistors with submicron channel lengths is described. A thin polymer film is spin coated on a prepatterned resist with a low resolution to create a thickness contrast in the overcoated polymer layer. After plasma and solvent etching, a submicron-sized line structure, which templates the contour of the prepattern, is obtained. A further lift-off process is applied to define source-drain electrodes of transistors. With a combination of ink-jet printing, transistors with channel length down to 400 nm have been fabricated by this method. We show that drive current density increases as expected, while the on/off current ratio 106 is achieved. © 2005 American Institute of Physics.

Performance prediction of graphene nanoribbon and carbon nanotube transistors

Carbon nanotubes (CNTs) and graphene nanoribbons (GNRs) field-effect transistor (FET) can be the basis for a quasi-one- dimensional (Q1D) transistor technology. Recent experiments show that the on-off ratio for GNR devices can be improved to level exploration of transistor action is justified. Here we use the tight-binding energy dipersion approximation, to assess the performance of semiconducting CNT and GNR is qualitatively in terms of drain current drive strength, bandgap and density of states for a specified device. By reducing the maximum conductance 4e2/h by half, we observed that our model has a particularly good fit with 50 nm channel single walled carbon nanotube (SWCNT) experimental data. Given the same bandgap, CNTs outperform GNRs due to valley degeneracy. Nevertheless, the variation of the device contacts will decide which transistor will exhibit better conductivity and thus higher ON currents. © 2011 American Institute of Physics.

Effect of gate dielectric scaling in nanometer scale vertical thin film transistors

A short channel vertical thin film transistor (VTFT) with 30 nm SiN x gate dielectric is reported for low voltage, high-resolution active matrix applications. The device demonstrates an ON/OFF current ratio as high as 10 9, leakage current in the fA range, and a sub-threshold slope steeper than 0.23 V/dec exhibiting a marked improvement with scaling of the gate dielectric thickness. © 2011 American Institute of Physics.

NEMS based logic and memory circuits

Carbon nanotube (CNT) based nano electromechanical system (NEMS) were developed to apply to the logic and the memory circuit. The electrical 'on-off' behavior induced by the mechanical movements of CNTs can promise low power consumption in circuit with very low level leakage current. Additionally, the unique vertical structure of nanotubes allows high integration density for devices. © 2012 IEEE.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. © 2012 Tan et al.

Linear semiconductor optical amplifiers

The chapter reviews properties and applications of linear semiconductor optical amplifiers (SOA). Section 12.1 covers SOA basics, including working principles, material systems, structures and their growth. Booster or inline amplifiers as well as low-noise preamplifiers are classified. Section 12.2 discusses the influence of parameters like gain, noise figure, gain saturation, gain and phase dynamics, and alpha-factor. In Sect. 12.3, the application of a linear SOA as a reach extender in future access networks is addressed. The input power dynamic range is introduced, and measurements for on-off keying and phase shift keying signals are shown. Section 12.4 presents the state of the art for commercially available SOA and includes a treatment of reflective SOAs (RSOA) as well. © 2012 Springer-Verlag Berlin Heidelberg.

Tunable Rashba effect in two-dimensional LaOBiS2 films: Ultrathin candidates for spin field effect transistors

Rashba spin splitting is a two-dimensional (2D) relativistic effect closely related to spintronics. However, so far there is no pristine 2D material to exhibit enough Rashba splitting for the fabrication of ultrathin spintronic devices, such as spin field effect transistors (SFET). On the basis of first-principles calculations, we predict that the stable 2D LaOBiS2 with only 1 nm of thickness can produce remarkable Rashba spin splitting with a magnitude of 100 meV. Because the medium La2O2 layer produces a strong polar field and acts as a blocking barrier, two counter-helical Rashba spin polarizations are localized at different BiS 2 layers. The Rashba parameter can be effectively tuned by the intrinsic strain, while the bandgap and the helical direction of spin states sensitively depends on the external electric field. We propose an advanced Datta-Das SFET model that consists of dual gates and 2D LaOBiS2 channels by selecting different Rashba states to achieve the on-off switch via electric fields. © 2013 American Chemical Society.

Analysis on the off-state design and characterization of LIGBTs in partial SOI technology

Classical high voltage devices fabricated on SOI substrates suffer from a backside coupling effect which could result in premature breakdown. This phenomenon becomes more prominent if the structure is an IGBT which features a p-type injector. To suppress the premature breakdown due to crowding of electro-potential lines within a confined SOI/buried oxide structure, the partial SOI (PSOI) technique is being introduced. This paper analyzes the off-state behavior of an n-type Superjunction (SJ) LIGBT fabricated on PSOI substrate. During the initial development stage the SJ LIGBT was found to have very high leakage. This was attributed to the back and side coupling effects. This paper discusses these effects and shows how this problem could be successfully addressed with minimal modifications of device layout. The off-state performance of the SJ LIGBT at different temperatures is assessed and a comparison to an equivalent LDMOSFET is given. © 2014 Elsevier Ltd. All rights reserved.