Free space adaptive optical interconnect, using a ferroelectric liquid crystal SLM for beam steering

A free-space, board-to-board, adaptive optical interconnect demonstrator has been developed. Binary phase gratings displayed on a Ferroelectric Liquid Crystal Spatial Light Modulator are used to maintain data transfer at 1.25Gbps, given varying optical misalignment © 2005 Optical Society of America.

Complementary metal-oxide-semiconductor-compatible and self-aligned catalyst formation for carbon nanotube synthesis and interconnect fabrication

We have for the first time developed a self-aligned metal catalyst formation process using fully CMOS (complementary metal-oxide-semiconductor) compatible materials and techniques, for the synthesis of aligned carbon nanotubes (CNTs). By employing an electrically conductive cobalt disilicide (CoSi 2) layer as the starting material, a reactive ion etch (RIE) treatment and a hydrogen reduction step are used to transform the CoSi 2 surface into cobalt (Co) nanoparticles that are active to catalyze aligned CNT growth. Ohmic contacts between the conductive substrate and the CNTs are obtained. The process developed in this study can be applied to form metal nanoparticles in regions that cannot be patterned using conventional catalyst deposition methods, for example at the bottom of deep holes or on vertical surfaces. This catalyst formation method is crucially important for the fabrication of vertical and horizontal interconnect devices based on CNTs. © 2012 American Institute of Physics.

Cost-effective 10 Gb/s polymer-based chip-to-chip optical interconnect

Board-level optical links are an attractive alternative to their electrical counterparts as they provide higher bandwidth and lower power consumption at high data rates. However, on-board optical technology has to be cost-effective to be commercially deployed. This study presents a chip-to-chip optical interconnect formed on an optoelectronic printed circuit board that uses a simple optical coupling scheme, cost-effective materials and is compatible with well-established manufacturing processes common to the electronics industry. Details of the link architecture, modelling studies of the link's frequency response, characterisation of optical coupling efficiencies and dynamic performance studies of this proof-of-concept chip-to-chip optical interconnect are reported. The fully assembled link exhibits a -3 dBe bandwidth of 9 GHz and -3 dBo tolerances to transverse component misalignments of ±25 and ±37 μm at the input and output waveguide interfaces, respectively. The link has a total insertion loss of 6 dBo and achieves error-free transmission at a 10 Gb/s data rate with a power margin of 11.6 dBo for a bit-error-rate of 10 -12. The proposed architecture demonstrates an integration approach for high-speed board-level chip-to-chip optical links that emphasises component simplicity and manufacturability crucial to the migration of such technology into real-world commercial systems. © 2012 The Institution of Engineering and Technology.

Free space adaptive optical interconnect, using a ferroelectric liquid crystal SLM for beam steering

A free-space, board-to-board, adaptive optical interconnect demonstrator has been developed. Binary phase gratings displayed on a Ferroelectric Liquid Crystal Spatial Light Modulator are used to maintain data transfer at 1.25Gbps, given varying optical misalignment.© 2005 Optical Society of America.

High temperature direct double side cooled inverter module for hybrid electric vehicle application

In this paper a novel approach to the design and fabrication of a high temperature inverter module for hybrid electrical vehicles is presented. Firstly, SiC power electronic devices are considered in place of the conventional Si devices. Use of SiC raises the maximum practical operating junction temperature to well over 200°C, giving much greater thermal headroom between the chips and the coolant. In the first fabrication, a SiC Schottky barrier diode (SBD) replaces the Si pin diode and is paired with a Si-IGBT. Secondly, double-sided cooling is employed, in which the semiconductor chips are sandwiched between two substrate tiles. The tiles provide electrical connections to the top and the bottom of the chips, thus replacing the conventional wire bonded interconnect. Each tile assembly supports two IGBTs and two SBDs in a half-bridge configuration. Both sides of the assembly are cooled directly using a high-performance liquid impingement system. Specific features of the design ensure that thermo-mechanical stresses are controlled so as to achieve long thermal cycling life. A prototype 10 kW inverter module is described incorporating three half-bridge sandwich assemblies, gate drives, dc-link capacitance and two heat-exchangers. This achieves a volumetric power density of 30W/cm3.

Standard cell automated layout for a CMOS 50 MHz 8 × 8 bit pipelined parallel dadda multiplier

An 8 × 8 pipelined parallel multiplier which uses the Dadda scheme is presented. The multiplier has been implemented in a 3-μm n-well CMOS process with two layers of metal using a standard cell automatic placement and routing program. The design uses a form of pipelined carry look-ahead adder in the final stage of summation, thus providing a significant contribution to the high performance of the multiplier. The design is expected to operate at a clock frequency of at least 50 MHz and has a flush time of seven clock cycles. The design illustrates a possible method of implementing an irregular architecture in VLSI using multiple levels of low-resistance, low-capacitance interconnect and automated layout techniques.

Novel architecture to facilitate disassembly and reuse of electronic components and sub-assemblies

This paper advances the proposition that in many electronic products, the partitioning scheme adopted and the interconnection system used to interconnect the sub-assemblies or components are intimately related to the economic benefits, and hence the attractiveness, of reuse of these items. An architecture has been developed in which the residual values of the connectors, components and sub-assemblies are maximized, and opportunities for take-back and reuse of redundant items are greatly enhanced. The system described also offers significant manufacturing cost benefits in terms of ease of assembly, compactness and robustness.

Performance of 10 Gbit/s VCSELs operating at 85°C

Oxide-confined VCSELs that are able to operate at modulation speeds of 10 Gbit/s at operating temperatures up to 85°C are demonstrated. This level of performance makes these VCSELs attractive sources for commercial applications in the computer interconnect industry.

Performance and power dissipation comparisons between 28 Gb/s NRZ, PAM, CAP and optical OFDM systems for data communication applications

Theoretical investigations have been carried out to analyze and compare the link power budget and power dissipation of non-return-to-zero (NRZ), pulse amplitude modulation-4 (PAM-4), carrierless amplitude and phase modulation-16 (CAP-16) and 16-quadrature amplitude modulation-orthogonal frequency division multiplexing (16-QAM-OFDM) systems for data center interconnect scenarios. It is shown that for multimode fiber (MMF) links, NRZ modulation schemes with electronic equalization offer the best link power budget margins with the least power dissipation for short transmission distances up to 200 m; while OOFDM is the only scheme which can support a distance of 300 m albeit with power dissipation as high as 4 times that of NRZ. For short single mode fiber (SMF) links, all the modulation schemes offer similar link power budget margins for fiber lengths up to 15 km, but NRZ and PAM-4 are preferable due to their system simplicity and low power consumption. For lengths of up to 30 km, CAP-16 and OOFDM are required although the schemes consume 2 and 4 times as much power respectively compared to that of NRZ. OOFDM alone allows link operation up to 35 km distances. © 1983-2012 IEEE.