Temperature dependent electron transport in amorphous oxide semiconductor thin film transistors

A temperature-dependent mobility model in amorphous oxide semiconductor (AOS) thin film transistors (TFTs) extracted from measurements of source-drain terminal currents at different gate voltages and temperatures is presented. At low gate voltages, trap-limited conduction prevails for a broad range of temperatures, whereas variable range hopping becomes dominant at lower temperatures. At high gate voltages and for all temperatures, percolation conduction comes into the picture. In all cases, the temperature-dependent mobility model obeys a universal power law as a function of gate voltage. © 2011 IEEE.

Polymer gate dielectrics with self-assembled monolayers for high-mobility organic thin-film transistors based on copper phthalocyanine

Organic thin-film transistors based on polycrystalline copper phthalocyanine (CuPc) were fabricated by using poly(vinyl alcohol) as gate dielectric. After treatment of the gate dielectric using an octadecyltrichlorosilane self-assembled monolayer, a mobility of up to 0.11 cm2/V∈s was achieved, which is comparable to that of single-crystal CuPc devices (0.1-1 cm2/V∈s). The surface morphology was analyzed and the possible reasons for the enhanced mobility are discussed. © 2009 Springer-Verlag.

High performance nanocomposite thin film transistors with bilayer carbon nanotube-polythiophene active channel by ink-jet printing

Nanocomposite thin film transistors (TFTs) based on nonpercolating networks of single-walled carbon nanotubes (CNTs) and polythiophene semiconductor [poly [5, 5′ -bis(3-dodecyl-2-thienyl)- 2, 2′ -bithiophene] (PQT-12)] thin film hosts are demonstrated by ink-jet printing. A systematic study on the effect of CNT loading on the transistor performance and channel morphology is conducted. With an appropriate loading of CNTs into the active channel, ink-jet printed composite transistors show an effective hole mobility of 0.23 cm 2 V-1 s-1, which is an enhancement of more than a factor of 7 over ink-jet printed pristine PQT-12 TFTs. In addition, these devices display reasonable on/off current ratio of 105-10 6, low off currents of the order of 10 pA, and a sharp subthreshold slope (<0.8 V dec-1). The work presented here furthers our understanding of the interaction between polythiophene polymers and nonpercolating CNTs, where the CNT density in the bilayer structure substantially influences the morphology and transistor performance of polythiophene. Therefore, optimized loading of ink-jet printed CNTs is crucial to achieve device performance enhancement. High performance ink-jet printed nanocomposite TFTs can present a promising alternative to organic TFTs in printed electronic applications, including displays, sensors, radio-frequency identification (RFID) tags, and disposable electronics. © 2009 American Institute of Physics.

Conduction bottleneck in silicon nanochain single electron transistors operating at room temperature

Single electron transistors are fabricated on single Si nanochains, synthesised by thermal evaporation of SiO solid sources. The nanochains consist of one-dimensional arrays of ~10nm Si nanocrystals, separated by SiO 2 regions. At 300 K, strong Coulomb staircases are seen in the drain-source current-voltage (I ds-V ds) characteristics, and single-electron oscillations are seen in the drain-source current-gate voltage (I ds-V ds) characteristics. From 300-20 K, a large increase in the Coulomb blockade region is observed. The characteristics are explained using singleelectron Monte Carlo simulation, where an inhomogeneous multiple tunnel junction represents a nanochain. Any reduction in capacitance at a nanocrystal well within the nanochain creates a conduction " bottleneck", suppressing current at low voltage and improving the Coulomb staircase. The single-electron charging energy at such an island can be very high, ~20k BT at 300 K. © 2012 The Japan Society of Applied Physics.

Electron-beam patterning of polymer electrolyte films to make multiple nanoscale gates for nanowire transistors

We report an electron-beam based method for the nanoscale patterning of the poly(ethylene oxide)/LiClO4 polymer electrolyte. We use the patterned polymer electrolyte as a high capacitance gate dielectric in single nanowire transistors and obtain subthreshold swings comparable to conventional metal/oxide wrap-gated nanowire transistors. Patterning eliminates gate/contact overlap, which reduces parasitic effects and enables multiple, independently controllable gates. The method's simplicity broadens the scope for using polymer electrolyte gating in studies of nanowires and other nanoscale devices. © 2013 American Chemical Society.

Semi-insulating layer for novel high voltage polysilicon thin film transistors

This work describes the deposition and characterisation of semi-insulating oxygen-doped silicon films for the development of high voltage polycrystalline silicon (poly-Si) circuitry on glass. The performance of a novel poly-Si High Voltage Thin Film Transistor (HVTFT) structure, incorporating a layer of semi-insulating material, has been investigated using a two dimensional device simulator. The semi-insulating layer increases the operating voltage of the HVTFT structure by linearising the potential distribution in the device offset region. A glass compatible semi-insulating layer, suitable for HVTFT applications, has been deposited by the Plasma Enhanced Chemical Vapour Deposition (PECVD) technique from silane (SiH4), nitrous oxide (N2O) and helium (He) gas mixtures. The as-deposited films are furnace annealed at 600°C which is the maximum process temperature. By varying the N2O/SiH4 ratio the conductivity of the annealed films can be accurately controlled up to a maximum of around 10-7 Ω-1cm-1. Helium dilution of the reactant gases improves both film uniformity and reproducibility. Raman analysis shows the as-deposited and annealed films to be completely amorphous. A model for the microstructure of these Semi-Insulating Amorphous Oxygen-Doped Silicon (SIAOS) films is proposed to explain the observed physical and electrical properties.

High rate deposition of ta-C:H using an electron cyclotron wave resonance plasma source

A compact electron cyclotron wave resonance (ECWR) source has been developed for the high rate deposition of hydrogenated tetrahedral amorphous carbon (ta-C:H). The ECWR provides growth rates of up to 1.5 nm/s over a 4-inch diameter and an independent control of the deposition rate and ion energy. The ta-C:H was deposited using acetylene as the source gas and was characterized as having an sp3 content of up to 77%, plasmon energy of 27 eV, refractive index of 2.45, hydrogen content of about 30%, optical gap of up to 2.1 eV and RMS surface roughness of 0.04 nm. © 1999 Elsevier Science S.A. All rights reserved.

High rate deposition of Ta-C:H using an electron cyclotron wave resonance plasma source

A compact electron cyclotron wave resonance (ECWR) source has been developed for the high rate deposition of hydrogenated tetrahedral amorphous carbon (ta-C:H). The ECWR provides growth rates of up to 900 angstrom/min and an independent control of the deposition rate and ion energy. The ta-C:H was deposited using acetylene as the source gas and was characterized in terms of its bonding, stress and friction coefficient. The results indicated that the ta-C:H produced using this source fulfills the necessary requirements for applications requiring enhanced tribological performance.

Advantages of top-gate, high-k dielectric carbon nanotube field-effect transistors

The subthreshold slope, transconductance, threshold voltage, and hysteresis of a carbon nanotube field-effect transistor (CNT FET) were examined as its configuration was changed from bottom-gate exposed channel, bottom-gate covered channel to top-gate FET. An individual single wall CNT was grown by chemical vapor deposition and its gate configuration was changed while determining its transistor characteristics to ensure that the measurements were not a function of different chirality or diameter CNTs. The bottom-gate exposed CNT FET utilized 900 nm SiO2 as the gate insulator. This CNT FET was then covered with TiO2 to form the bottom-gate covered channel CNT FET. Finally, the top-gate CNT FET was fabricated and the device utilized TiO 2 (K ∼ 80, equivalent oxide thickness=0.25 nm) as the gate insulator. Of the three configurations investigated, the top-gate device exhibited best subthreshold slope (67-70 mV/dec), highest transconductance (1.3 μS), and negligible hysteresis in terms of threshold voltage shift. © 2006 American Institute of Physics.