Impact of high-k dielectrics on breakdown performances of SiC and diamond Schottky diodes

This paper presents a comparison between SiC and diamond Schottky barrier diodes using the oxide ramp termination. The influences of the dielectric thickness and relative permittivity on the diode's electrical performance are investigated. Typical commercial drift layer parameters are used for this study. The extension of the space charge area throughout the drift region and the current distribution at breakdown are shown. The efficiency of the termination is also evaluated for both SiC and diamond diodes. © (2009) Trans Tech Publications, Switzerland.

Fabrication of diamond based schottky barrier diodes with oxide ramp termination

The paper's goal is the first demonstration of the fabrication of high power Schottky diodes on synthetic diamond using oxide ramp termination. In order to allow full activated impurities at room temperature and a high hole mobility a low boron doping of the drift layer is employed. Several aspects of the manufacturing technology are presented. A termination with a small ramp angle can be obtained using only RIE technique due to diamond wafer nonuniformity (roughness). Experimental forward and reverse characteristics measured on diamond diodes are also included. © 2007 IEEE.

Tunable hydrodynamic chromatography of microparticles localized in short microchannels.

This paper describes a new way to perform hydrodynamic chromatography (HDC) for the size separation of particles based on a unique recirculating flow pattern. Pressure-driven (PF) and electro-osmotic flows (EOF) are opposed in narrow glass microchannels that expand at both ends. The resulting bidirectional flow turns into recirculating flow because of nonuniform microchannel dimensions. This hydrodynamic effect, combined with the electrokinetic migration of the particles themselves, results in a trapping phenomenon, which we have termed flow-induced electrokinetic trapping (FIET). In this paper, we exploit recirculating flow and FIET to perform a size-based separation of samples of microparticles trapped in a short separation channel using a HDC approach. Because these particles have the same charge (same zeta potential), they exhibit the same electrophoretic mobility, but they can be separated according to size in the recirculating flow. While trapped, particles have a net drift velocity toward the low-pressure end of the channel. When, because of a change in the externally applied PF or electric field, the sign of the net drift velocity reverses, particles can escape the separation channel in the direction of EOF. Larger particles exhibit a larger net drift velocity opposing EOF, so that the smaller particles escape the separation channel first. In the example presented here, a sample plug containing 2.33 and 2.82 microm polymer particles was introduced from the inlet into a 3-mm-long separation channel and trapped. Through tuning of the electric field with respect to the applied PF, the particles could be separated, with the advantage that larger particles remained trapped. The separation of particles with less than 500 nm differences in diameter was performed with an analytical resolution comparable to that of baseline separation in chromatography. When the sample was not trapped in the separation channel but located further downstream, separations could be carried out continuously rather than in batch. Smaller particles could successfully pass through the separation channel, and particles were separated by size. One of the main advantages of exploiting FIET for HDC is that this method can be applied in quite short (a few millimeters) channel geometries. This is in great contrast to examples published to date for the separation of nanoparticles in much longer micro- and nanochannels.

Feasibility of AlGaInAs lasers for high speed uncooled communication systems

The feasibility of using AlGaInAs lasers for high-speed modulation at high temperatures was evaluated and compared with performance of GaInAsP devices. Both drift-diffusion and rate equation simulation were involved so that the temperature dependence of material parameters was found in terms of overall dynamic performance. Differential gain was estimated by means of drift-diffusion simulations.

Analysis of the mechanisms for impaired high-temperature, high-speed performance of 1.3 μm InGaAsP lasers

In this paper, the static and dynamic performance of multi quantum-well (MQW) 1.3 μm InGaAsP Fabry Perot lasers is assessed experimentally and theoretically to identify the mechanisms responsible for impaired high speed performance at elevated temperature. Initially, threshold currents and spontaneous emission spectra are characterized for a range of temperatures from room temperature to 85 °C to indicate a significant increase in non-radiative current contributions. Preliminary estimates are made for the contributions of leakage and Auger recombination rates, found from the dependence of integrated spontaneous emission with carrier density. Drift-diffusion modelling is found to accurately predict the trend of threshold currents over temperature. Using gain modelling good agreement is found between the measured and predicted integrated spontaneous emission intensity. Gain measurements at 85 °C indicate a reduction in RIN frequency to 63% of the 25 °C value which matches well with experimental small signal performance.

Analytical model for the 3D-RESURF effect

This paper presents an analytical model for the determination of the basic breakdown properties of three-dimensional (3D)-RESURF/CoolMOS/super junction type structures. To account for the two-dimensional (2D) effect of the 3D-RESURF action, 2D models of the electric field distribution are developed. Based on these, expressions are derived for the breakdown voltage as a function of doping concentration and physical dimensions. In addition to cases where the drift regions are fully depleted, the model developed is also applicable to situations involving drift regions which are almost depleted. Accuracy of the analytical approach is verified by comparison with numerical results obtained from the MEDICI device simulator.

Modeling of MOS-side carrier injection in trench-gate IGBTs

A compact trench-gate IGBT model that captures MOS-side carrier injection is developed. The model retains the simplicity of a one-dimensional solution to the ambipolar diffusion equation, but at the same time captures MOS-side carrier injection and its effects on steady-state carrier distribution in the drift region and on switching waveforms. © 2007 IEEE.

Spice modelling of the superjunction IGBT

This paper presents a SPICE model of the SuperJunction Insulated Gate Bipolar Transistor (SJIGBT) [1]. SPICE simulation results are in good agreement with the DESSIS simulation results under DC conditions. This model consists of an intrinsic MOSFET and a parallel combination of a wide and a narrow base pnp BJTs. A parasitic JFET is also included to account for the restricted current flow between two adjacent p-wells. In addition the JFET component also models the additional depletion region caused by the transverse junction at the upper side of the n-drift region where the current is mainly transported via majority carriers.

How much do we spend to save? Calculating the embodied carbon costs of retrofit

The drive to reduce carbon emissions from domestic housing has led to a recent shift of focus from new-­‐build to retrofit. However there are two significant differences. Firstly more work is needed to retrofit existing housing to the same energy efficiency standards as new-­‐build. Secondly the remaining length of service life is potentially shorter. This implies that the capital expenditure – both financial and carbon -­‐ of retrofit may be disproportionate to the savings gained over the remaining life. However the Government’s definition of low and zero carbon continues to exclude the capital (embodied) carbon costs of construction, which has resulted in a lack of data for comparison. The paper addresses this gap by reporting the embodied carbon costs of retrofitting four individual pilot properties in Rampton Drift, part of an Eco-­‐Town Demonstrator Project in Cambridgeshire. Through collecting details of the materials used and their journeys from manufacturer to site, the paper conducts a ‘cradle-­‐to-­‐gate’ life cycle carbon assessment for each property. The embodied carbon figures are calculated using a software tool being developed by the Centre for Sustainable Development at the University of Cambridge. The key aims are to assess the real embodied carbon costs of retrofit of domestic properties, and to test the new tool; it is hoped that the methodology, the tool and the specific findings will be transferable to other projects. Initial changes in operational energy as a result of the retrofit works will be reported and compared with the embodied carbon costs when presenting this paper.

Perceptual learning, roving and the unsupervised bias

Perceptual learning improves perception through training. Perceptual learning improves with most stimulus types but fails when . certain stimulus types are mixed during training (roving). This result is surprising because classical supervised and unsupervised neural network models can cope easily with roving conditions. What makes humans so inferior compared to these models? As experimental and conceptual work has shown, human perceptual learning is neither supervised nor unsupervised but reward-based learning. Reward-based learning suffers from the so-called unsupervised bias, i.e., to prevent synaptic " drift" , the . average reward has to be exactly estimated. However, this is impossible when two or more stimulus types with different rewards are presented during training (and the reward is estimated by a running average). For this reason, we propose no learning occurs in roving conditions. However, roving hinders perceptual learning only for combinations of similar stimulus types but not for dissimilar ones. In this latter case, we propose that a critic can estimate the reward for each stimulus type separately. One implication of our analysis is that the critic cannot be located in the visual system. © 2011 Elsevier Ltd.

Design and optimization of a 250nm SOI LDMOSFET

This work is aimed at optimising the static performance of a high voltage SOI LDMOSFET. Starting with a conventional LDMOSFET, 2D and 3D numerical simulation models, able to accurately match datasheet values, have been developed. Moving from the original device, several design techniques have been investigated with the target of improving the breakdown voltage and the ON-state resistance. The considered design techniques are based on the modification of the doping profile of the drift region and the Superjunction design technique. The paper shows that a single step doping within the drift region is the best design choice for the considered device and is found to give a 24% improvement in the breakdown voltage and a 17% reduction of the ON-state resistance. © 2011 IEEE.

Low on-resistance SOI dual-trench-gate MOSFET

A low specific on-resistance (R-{{\rm on}, {\rm sp}}) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation. The SOI MOSFET features double trenches and dual gates (DTDG SOI): an oxide trench in the drift region, a buried gate inset in the oxide trench, and another trench gate (TG) extended to a buried oxide layer. First, the dual gates form dual conduction channels, and the extended gate widens the vertical conduction area; both of which sharply reduce R-{{\rm on}, {\rm sp}}. Second, the oxide trench folds the drift region in the vertical direction, resulting in a reduced device pitch and R-{{\rm on}, {\rm sp}}. Third, the oxide trench causes multidirectional depletion. This not only enhances the reduced surface field effect and thus reshapes the electric field distribution but also increases the drift doping concentration, leading to a reduced R-{{\rm on}, {\rm sp}} and an improved breakdown voltage (BV). Compared with a conventional SOI lateral Double-diffused metal oxide semiconductor (LDMOS), the DTDG MOSFET increases BV from 39 to 92 V at the same cell pitch or decreases R-{{\rm on}, { \rm sp}} by 77% at the same BV by simulation. Finally, the TG extended synchronously acts as an isolation trench between the high/low-voltage regions in a high-voltage integrated circuit, saving the chip area and simplifying the isolation process. © 2006 IEEE.

Paradoxical evidence integration in rapid decision processes

Decisions about noisy stimuli require evidence integration over time. Traditionally, evidence integration and decision making are described as a one-stage process: a decision is made when evidence for the presence of a stimulus crosses a threshold. Here, we show that one-stage models cannot explain psychophysical experiments on feature fusion, where two visual stimuli are presented in rapid succession. Paradoxically, the second stimulus biases decisions more strongly than the first one, contrary to predictions of one-stage models and intuition. We present a two-stage model where sensory information is integrated and buffered before it is fed into a drift diffusion process. The model is tested in a series of psychophysical experiments and explains both accuracy and reaction time distributions. © 2012 Rüter et al.

200-V lateral superjunction LIGBT on partial SOI

This letter presents a novel lateral superjunction lateral insulated-gate bipolar transistor (LIGBT) in partial silicon-on-insulator (SOI) technology in 0.18-μm partial-SOI (PSOI) high-voltage (HV) process. For an n-type superjunction LIGBT, the p-layer in the superjunction drift region not only helps in achieving uniform electric field distribution but also contributes to the on-state current. The superjunction LIGBT successfully achieves a breakdown voltage (BV) of 210 V with an R dson of 765 mΩ ̇ mm 2. It exhibits half the value of specific on-state resistance R dson and three times higher saturation current (I dsat) for the same BV, compared to a comparable lateral superjunction laterally diffused metal-oxide-semiconductor fabricated in the same technology. It also performs well in higher temperature dc operation with 38.8% increase in R dson at 175°C, compared to the room temperature without any degradation in latch-up performance. To realize this device, it only requires one additional mask layer into X-FAB 0.18-μm PSOI HV process. © 2012 IEEE.

Superjunction IGBT filling the gap between SJ MOSFET and ultrafast IGBT

In this letter, we report E off-versus-V ce tradeoff curves for vertical superjunction insulated-gate bipolar transistors (SJ IGBTs), exhibiting unusual inverse slopes dE off/dV ce > 0 in a transition region between purely unipolar and strongly bipolar device behaviors. This effect is due to the action of p-pillar hole current when depleting the drift layer of SJ IGBTs during turnoff and the impact of current gain on the transconductance. Such SJ IGBTs surpass by a very significant margin their superjunction MOSFET counterparts in terms of power-handling capability and on-state and turnoff losses, all at the same time. © 2012 IEEE.