90 resultados para TUNGSTEN CARBIDE


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Sintered boron carbide is very hard, and can be an attractive material for wear-resistant components in critical applications. Previous studies of the erosion of less hard ceramics have shown that their wear resistance depends on the nature of the abrasive particles. Erosion tests were performed on a sintered boron carbide ceramic with silica, alumina and silicon carbide erodents. The different erodents caused different mechanisms of erosion, either by lateral cracking or small-scale chipping; the relative values of the hardness of the erodent and the target governed the operative mechanism. The small-scale chipping mechanism led to erosion rates typically an order of magnitude lower than the lateral fracture mechanism. The velocity exponents for erosion in the systems tested were similar to those seen in other work, except that measured with the 125 to 150 μm silica erodent. With this erodent the exponent was initially high, then decreased sharply with increasing velocity and became negative. It was proposed that this was due to deformation and fragmentation of the erodent particles. In the erosion testing of ceramics, the operative erosion mechanism is important. Care must be taken to ensure that the same mechanism is observed in laboratory testing as that which would be seen under service conditions, where the most common erodent is silica.

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The motivation for our work is to identify a space for silicon carbide (SiC) devices in the silicon (Si) world. This paper presents a detailed experimental investigation of the switching behaviour of silicon and silicon carbide transistors (a JFET and a cascode device comprising a Si-MOSFET and a SiC-JFET). The experimental method is based on a clamped inductive load chopper circuit that puts considerable stress on the device and increases the transient power dissipation. A precise comparison of switching behaviour of Si and SiC devices on similar terms is the novelty of our work. The cascode is found to be an attractive fast switching device, capable of operating in two different configurations whose switching equivalent circuits are proposed here. The effect of limited dv/dt of the Si-MOSFET on the switching of the SiC-JFET in a cascode is also critically analysed.

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This paper focuses on the PSpice model of SiC-JFET element inside a SiCED cascode device. The device model parameters are extracted from the I-V and C-V characterization curves. In order to validate the model, an inductive test rig circuit is designed and tested. The switching loss is estimated both using oscilloscope and calorimeter. These results are found to be in good agreement with the simulated results.