Elastic properties of crystalline-amorphous core-shell silicon nanowires

The pressure behavior of Raman frequencies and line widths of crystalline core-amorphous shell silicon nanowires (SiNWs) with two different core-to-shell ratio thicknesses was studied at pressures up to 8 GPa. The obtained isothermal compressibility (bulk modulus) of SiNWs with a core-to-shell ratio of about 1.8 is ∼20% higher (lower) than reported values for bulk Si. For SiNWs with smaller core-to-shell ratios, a plastic deformation of the shell was observed together with a strain relaxation. A significant increase in the full width at half-maximum of the Raman LTO-peak due to phonon decay was used to determine the critical pressure at which LTO-phonons decay into LO + TA phonons. Our results reveal that this critical pressure in strained core-shell SiNWs (∼4 GPa) is different from the reported value for bulk Si (∼7 GPa), whereas no change is observed for relaxed core-shell SiNWs. © 2013 American Chemical Society.

Formation of composite organic thin film transistors with nanotubes and nanowires

Plastic electronics is a rapidly expanding topic, much of which has been focused on organic semiconductors. However, it is also of interest to find viable ways to integrate nanomaterials, such as silicon nanowires (SiNWs) and carbon nanotubes (CNTs), into this technology. Here, we present methods of fabrication of composite devices incorporating such nanostructured materials into an organic matrix. We investigate the formation of polymer/CNT composites, for which we use the semiconducting polymer poly(3,3‴-dialkyl-quaterthiophene) (PQT). We also report a method of fabricating polymer/SiNW TFTs, whereby sparse arrays of parallel oriented SiNWs are initially prepared on silicon dioxide substrates from forests of as-grown gold-catalysed SiNWs. Subsequent ink-jet printing of PQT on these arrays produces a polymer/SiNW composite film. We also present the electrical characterization of all composite devices. © 2007 Elsevier B.V. All rights reserved.

Engineering hierarchical nanostructures by elastocapillary self-assembly

Surfaces coated with nanoscale filaments such as silicon nanowires and carbon nanotubes are potentially compelling for high-performance battery and capacitor electrodes, photovoltaics, electrical interconnects, substrates for engineered cell growth, dry adhesives, and other smart materials. However, many of these applications require a wet environment or involve wet processing during their synthesis. The capillary forces introduced by these wet environments can lead to undesirable aggregation of nanoscale filaments, but control of capillary forces can enable manipulation of the filaments into discrete aggregates and novel hierarchical structures. Recent studies suggest that the elastocapillary self-assembly of nanofilaments can be a versatile and scalable means to build complex and robust surface architectures. To enable a wider understanding and use of elastocapillary self-assembly as a fabrication technology, we give an overview of the underlying fundamentals and classify typical implementations and surface designs for nanowires, nanotubes, and nanopillars made from a wide variety of materials. Finally, we discuss exemplary applications and future opportunities to realize new engineered surfaces by the elastocapillary self-assembly of nanofilaments. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Precursor flow rate manipulation for the controlled fabrication of twin-free GaAs nanowires on silicon substrates

Vertically oriented GaAs nanowires (NWs) are grown on Si(111) substrates using metal-organic chemical vapor deposition. Controlled epitaxial growth along the 111 direction is demonstrated following the deposition of thin GaAs buffer layers and the elimination of structural defects, such as twin defects and stacking faults, is found for high growth rates. By systematically manipulating the AsH 3 (group-V) and TMGa (group-III) precursor flow rates, it is found that the TMGa flow rate has the most significant effect on the nanowire quality. After capping the minimal tapering and twin-free GaAs NWs with an AlGaAs shell, long exciton lifetimes (over 700ps) are obtained for high TMGa flow rate samples. It is observed that the Ga adatom concentration significantly affects the growth of GaAs NWs, with a high concentration and rapid growth leading to desirable characteristics for optoelectronic nanowire device applications including improved morphology, crystal structure and optical performance. © 2012 IOP Publishing Ltd.

Taper-free and kinked germanium nanowires grown on silicon via purging and the two-temperature process

We investigate the growth procedures for achieving taper-free and kinked germanium nanowires epitaxially grown on silicon substrates by chemical vapor deposition. Singly and multiply kinked germanium nanowires consisting of 111 segments were formed by employing a reactant gas purging process. Unlike non-epitaxial kinked nanowires, a two-temperature process is necessary to maintain the taper-free nature of segments in our kinked germanium nanowires on silicon. As an application, nanobridges formed between (111) side walls of V-grooved (100) silicon substrates have been demonstrated. © 2012 IOP Publishing Ltd.

Vertically oriented epitaxial germanium nanowires on silicon substrates using thin germanium buffer layers.

We demonstrate a method to realize vertically oriented Ge nanowires on Si(111) substrates. Ge nanowires were grown by chemical vapor deposition using Au nanoparticles to seed nanowire growth via a vapor-liquid-solid growth mechanism. Rapid oxidation of Si during Au nanoparticle application inhibits the growth of vertically oriented Ge nanowires directly on Si. The present method employs thin Ge buffer layers grown at low temperature less than 600 degrees C to circumvent the oxidation problem. By using a thin Ge buffer layer with root-mean-square roughness of approximately 2 nm, the yield of vertically oriented Ge nanowires is as high as 96.3%. This yield is comparable to that of homoepitaxial Ge nanowires. Furthermore, branched Ge nanowires could be successfully grown on these vertically oriented Ge nanowires by a secondary seeding technique. Since the buffer layers are grown under moderate conditions without any high temperature processing steps, this method has a wide process window highly suitable for Si-based microelectronics.

Smart chemical sensor application of ZnO nanowires grown on CMOS compatible SOI microheater platform

Smart chemical sensor based on CMOS(complementary metal-oxide- semiconductor) compatible SOI(silicon on insulator) microheater platform was realized by facilitating ZnO nanowires growth on the small membrane at the relatively low temperature. Our SOI microheater platform can be operated at the very low power consumption with novel metal oxide sensing materials, like ZnO or SnO2 nanostructured materials which demand relatively high sensing temperature. In addition, our sol-gel growth method of ZnO nanowires on the SOI membrane was found to be very effective compared with ink-jetting or CVD growth techniques. These combined techniques give us the possibility of smart chemical sensor technology easily merged into the conventional semiconductor IC application. The physical properties of ZnO nanowire network grown by the solution-based method and its chemical sensing property also were reported in this paper.

Local synthesis and alignment of zinc oxide nanowires in aqueous solution using microheaters

A bottom-up technique for synthesizing transversely suspended zinc oxide nanowires (ZnO NWs) under a zinc nitrate (Zn(NO 3) 2· 6H 2O) and hexamethylenetetramine (HMTA, (CH 2) 6·N 4) solution within a microfabricated device is reported in this paper. The device consists of a microheater which is used to initially create an oxidized ZnO seed layer. ZnO NWs are then locally synthesized by the microheater and electrodes embedded within the devices are used to drive electric field directed horizontal alignment of the nanowires within the device. The entire process is carried out at low temperature. This approach has the potential to considerably simplify the fabrication and assembly of ZnO nanowires on CMOS compatible substrates, allowing for the chemical synthesis to be carried out under near-ambient conditions by locally defining the conditions for nanowire growth on a silicon reactor chip. © 2012 IEEE.

Revealing lithium-silicide phase transformations in nano-structured silicon-based lithium ion batteries via in situ NMR spectroscopy.

Nano-structured silicon anodes are attractive alternatives to graphitic carbons in rechargeable Li-ion batteries, owing to their extremely high capacities. Despite their advantages, numerous issues remain to be addressed, the most basic being to understand the complex kinetics and thermodynamics that control the reactions and structural rearrangements. Elucidating this necessitates real-time in situ metrologies, which are highly challenging, if the whole electrode structure is studied at an atomistic level for multiple cycles under realistic cycling conditions. Here we report that Si nanowires grown on a conducting carbon-fibre support provide a robust model battery system that can be studied by (7)Li in situ NMR spectroscopy. The method allows the (de)alloying reactions of the amorphous silicides to be followed in the 2nd cycle and beyond. In combination with density-functional theory calculations, the results provide insight into the amorphous and amorphous-to-crystalline lithium-silicide transformations, particularly those at low voltages, which are highly relevant to practical cycling strategies.