319 resultados para Posterior Layer


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We have used scanning gate microscopy to explore the local conductivity of a current-annealed graphene flake. A map of the local neutrality point (NP) after annealing at low current density exhibits micron-sized inhomogeneities. Broadening of the local e-h transition is also correlated with the inhomogeneity of the NP. Annealing at higher current density reduces the NP inhomogeneity, but we still observe some asymmetry in the e-h conduction. We attribute this to a hole-doped domain close to one of the metal contacts combined with underlying striations in the local NP. © 2010 American Institute of Physics.

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A power LDMOS on partial silicon on insulator (PSOI) with a variable low-κ dielectric (VLKD) buried layer and a buried p (BP) layer is proposed (VLKD BPSOI). At a low κ value, the electric field strength in the buried dielectric (EI) is enhanced, and a Si window makes the substrate share the vertical voltage drop, leading to a high vertical breakdown voltage (BV). Moreover, three interface field peaks are introduced by the BP, the Si window, and the VLKD, which modulate the fields in the SOI layer, the VLKD layer, and the substrate; consequently, a high BV is obtained. Furthermore, the BP reduces the specific on-resistance (Ron), and the Si window alleviates the self-heating effect (SHE). The BV for VLKD BPSOI is enhanced by 34.5%, and Ron is decreased by 26.6%, compared with those for the conventional PSOI, and VLKD BPSOI also maintains a low SHE. © 2006 IEEE.

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This work describes the deposition and characterisation of semi-insulating oxygen-doped silicon films for the development of high voltage polycrystalline silicon (poly-Si) circuitry on glass. The performance of a novel poly-Si High Voltage Thin Film Transistor (HVTFT) structure, incorporating a layer of semi-insulating material, has been investigated using a two dimensional device simulator. The semi-insulating layer increases the operating voltage of the HVTFT structure by linearising the potential distribution in the device offset region. A glass compatible semi-insulating layer, suitable for HVTFT applications, has been deposited by the Plasma Enhanced Chemical Vapour Deposition (PECVD) technique from silane (SiH4), nitrous oxide (N2O) and helium (He) gas mixtures. The as-deposited films are furnace annealed at 600°C which is the maximum process temperature. By varying the N2O/SiH4 ratio the conductivity of the annealed films can be accurately controlled up to a maximum of around 10-7 Ω-1cm-1. Helium dilution of the reactant gases improves both film uniformity and reproducibility. Raman analysis shows the as-deposited and annealed films to be completely amorphous. A model for the microstructure of these Semi-Insulating Amorphous Oxygen-Doped Silicon (SIAOS) films is proposed to explain the observed physical and electrical properties.

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Controlling the growth of ZnO nanostructures for photovoltaic applications will ensure greater device efficiency and parameter control. This paper reports on methods to engineer the morphology and tailor the nanostructure growth direction through the hydrothermal synthesis method. Effective control is achieved through the use of a sputtered zinc layer together with modifications of the growth solution. These nanostructures have been developed with a view to incorporation into excitonic solar cells, and methods to improve surface stability using a fully aqueous synthesis method will be discussed. © by Oldenbourg Wissenschaftsverlag, München.

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Various vortex generators which include ramp, split-ramp and a new hybrid concept "ramped-vane" are investigated under normal shock conditions with a diffuser at Mach number of 1.3. The dimensions of the computational domain were designed using Reynolds Average Navier-Stokes studies to be representative of the flow in an external-compression supersonic inlet. Using this flow geometry, various vortex generator concepts were studied with Implicit Large Eddy Simulation. In general, the ramped-vane provided increased vorticity compared to the other devices and reduced the separation length downstream of the device centerline. In addition, the size, edge gap and streamwise position respect to the shock were studied for the ramped-vane and it was found that a height of about half the boundary thickness and a large trailing edge gap yielded a fully attached flow downstream of the device. This ramped-vane also provided the largest reduction in the turbulent kinetic energy and pressure fluctuations. Additional benefits include negligible drag while the reductions in boundary layer displacement thickness and shape factor were seen compared to other devices. © 2010 by Sang Lee.

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Various vortex generators which include ramp, split-ramp and a new hybrid concept "ramped-vane" are investigated under normal shock conditions with a diffuser at Mach number of 1.3. The dimensions of the computational domain were designed using Reynolds Average Navier-Stokes studies to be representative of the flow in an external-compression supersonic inlet. Using this flow geometry, various vortex generator concepts were studied with Implicit Large Eddy Simulation. In general, the ramped-vane provided increased vorticity compared to the other devices and reduced the separation length downstream of the device centerline. In addition, the size, edge gap and streamwise position respect to the shock were studied for the ramped-vane and it was found that a height of about half the boundary thickness and a large trailing edge gap yielded a fully attached flow downstream of the device. This ramped-vane also provided the largest reduction in the turbulent kinetic energy and pressure fluctuations. Additional benefits include negligible drag while the reductions in boundary layer displacement thickness and shape factor were seen compared to other devices. © 2011 Elsevier Ltd.